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copyright ?2012 zilog ? , inc. all rights reserved. www.zilog.com ps025113-1212 product specification high-performance 8-b it microcontrollers z8 encore! ? f0830 series
ps025113-1212 disclaimer z8 encore! ? f0830 series product specification ii do not use this product in life support systems. life support policy zilog?s products are not authorized for use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical impl ant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signi ficant injury to the user. a criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support devi ce or system or to affect its safety or effectiveness. document disclaimer ?2012 zilog, inc. all rights reserved. information in this publication c oncerning the devices, applications or technology described is intend ed to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. z8, z8 encore! and z8 encore! xp are trademarks or registered trademarks of zilog, inc. all other product or service names are the property of their respective owners. warning:
ps025113-1212 revision history z8 encore! ? f0830 series product specification iii revision history each instance in this document?s revision history reflects a change from its previous edi- tion. for more details, refer to the corresponding page(s) or appropriate links furnished in the table below. date revision level chapter/section description page no. dec 2012 13 gpio modified gpio port d0 language in shared reset pin section and port alternate func- tion mapping table. 35 , 36 sep 2011 12 led drive enable register clarified statement surrounding the alternate function register as it relates to the led function; revised sector based flash protec- tion description; revised packaging chapter. 51 , 115 , 199 dec 2007 11 n/a updated all instances of z8 encore! xp f0830 to z8 encore! f0830 . all nov 2007 10 dc characteristics, on-chip peripheral ac and dc electri- cal characteristics updated tables 116 and and 122. 185 , 193 sep 2007 09 timers, pwm single out- put mode, pwm dual out- put mode, analog-to-digital converter, reference buffer. updated figures 2 and 4, table 4. 8 , 9 , 11 , 68 , 74 , 75 , 98 , 101 apr 2007 08 optimizing nvds memory usage for execution speed, on-chip peripheral ac and dc electrical characteristics added a note under table 93 in nonvolatile data storage chapter. updated table 121 and table 122 in electrical characteristics chapter. other style updates. 137 , 193 , 193 dec 2006 07 general purpose input/output added pd0 in table 16. 38 overview, interrupt controller changed the number of interrupts to 17. 1 , 5 , 53 nonvolatile data storage updated chapter. 136 oscillator control register defi- nitions, ac characteristics, on- chip peripheral ac and dc electrical characteristics updated tables 117 and 122. added figure 24. 156 , 189 , 193 ordering information updated part number suffix designations. 205 n/a removed preliminary stamp from footer. all
ps025113-1212 table of contents z8 encore! ? f0830 series product specification iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 nonvolatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 external crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 acronyms and expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ps025113-1212 table of contents z8 encore! ? f0830 series product specification v voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stop mode recovery using wdt time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 stop mode recovery using gpio port pin transition . . . . . . . . . . . . . . . . . . . . . . . 27 stop mode recovery usin g the external reset pin . . . . . . . . . . . . . . . . . . . . . . . 28 debug pin driven low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reset register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 peripheral level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 power control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 general purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 shared reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 crystal oscillator override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 port a?d address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 port a?d control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port a?d data direction subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port a?d alternate function subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 port a?d output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 led drive enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 led drive level high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 led drive level low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ps025113-1212 table of contents z8 encore! ? f0830 series product specification vi master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 shared interrupt select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 timer pin signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 timer 0?1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 timer 0?1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer reload unlo ck sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer control register defi nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 watchdog timer reload upper, high and low by te registers . . . . . . . . . . . . . . . 96 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 adc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 adc interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 internal voltage reference generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ps025113-1212 table of contents z8 encore! ? f0830 series product specification vii calibration and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 adc control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 sample settling time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 sample time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 comparator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 data memory address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 flash operation timing using the flash frequenc y registers . . . . . . . . . . . . . . . 114 flash code protection against external access . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 flash code protection against accidental prog ram and erasure . . . . . . . . . . . . . 114 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 nvds operational requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 option bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 flash option bit control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 trim bit address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 trim bit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 flash option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 nonvolatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ps025113-1212 table of contents z8 encore! ? f0830 series product specification viii operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 nvds code interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 power failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 optimizing nvds memory usage for execution speed . . . . . . . . . . . . . . . . . . . . 137 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ocd autobaud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 oscillator operation with an external rc network . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 op code maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
ps025113-1212 table of contents z8 encore! ? f0830 series product specification ix electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 190 general purpose i/o port input da ta sample timing . . . . . . . . . . . . . . . . . . . . . . 195 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 appendix a. register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 general purpose ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 low power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 led controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 16 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 17 comparator 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 18 gpio port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 trim bit control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 28 flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
ps025113-1212 list of figures z8 encore! ? f0830 series product specification x list of figures figure 1. z8 encore! f0830 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. z8f0830 series in 20-pin soic, ssop, pdip package . . . . . . . . . . . . . . . . 8 figure 3. z8f0830 series in 28-pin soic, ssop, pdip package . . . . . . . . . . . . . . . . 8 figure 4. z8f0830 series in 20-pin qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. z8f0830 series in 28-pin qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. voltage brown-out reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9. interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 11. analog-to-digital converter block diagram . . . . . . . . . . . . . . . . . . . . . . . 99 figure 12. adc timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 13. adc convert timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 14. 1k flash with nvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 15. 2k flash with nvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 16. 4k flash with nvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 17. 8k flash with nvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 18. 12k flash without nvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 19. flash controller operation flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 20. on-chip debugger block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 21. interfacing the on-chip debugg er?s dbg pin with an rs-232 interface, ? #1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 22. interfacing the on-chip debugg er?s dbg pin with an rs-232 interface, ? #2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 23. ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 24. oscillator control clock switching flow chart . . . . . . . . . . . . . . . . . . . . 156 figure 25. recommended 20 mhz crystal oscillato r configuration . . . . . . . . . . . . . 158 figure 26. connecting the on-chip oscillator to an external rc network . . . . . . . . 159
ps025113-1212 list of figures z8 encore! ? f0830 series product specification xi figure 27. typical rc oscilla tor frequency as a function of external capacitance ? with a 45 k ? resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 28. op code map cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 29. first op code map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 30. second op code map after 1fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 31. i cc versus system clock frequency (halt mode) . . . . . . . . . . . . . . . . 187 figure 32. i cc versus system clock frequency (normal mode) . . . . . . . . . . . . . 188 figure 33. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 34. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 35. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 36. flash current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xii list of tables table 1. z8 encore! f0830 series family part se lection guide . . . . . . . . . . . . . . . . . 2 table 2. acronyms and expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. z8 encore! f0830 series pa ckage options . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. pin characteristics (20- and 28-pin devices) . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. z8 encore! f0830 series program memory maps . . . . . . . . . . . . . . . . . . . 15 table 7. z8 encore! f0830 series flash memory information area map . . . . . . . . 16 table 8. register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. reset and stop mode recovery character istics and latency . . . . . . . . . . . 22 table 10. reset sources and resulting reset type . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. stop mode recovery so urces and resulting action . . . . . . . . . . . . . . . . . . 27 table 12. por indicator values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. reset status register (rststat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. power control register 0 (pwrctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. port availability by device and package type . . . . . . . . . . . . . . . . . . . . . . 33 table 16. port alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. gpio port registers and subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. port a?d gpio address registers (pxaddr) . . . . . . . . . . . . . . . . . . . . . 40 table 19. port control subregister access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. port a?d control registers (pxctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. port a?d data direction subregisters (px dd) . . . . . . . . . . . . . . . . . . . . . . 41 table 22. port a?d alternate functio n subregisters (pxaf) . . . . . . . . . . . . . . . . . . . 42 table 23. port a?d output control subregisters (pxoc) . . . . . . . . . . . . . . . . . . . . . 43 table 24. port a?d high drive enable subregisters (pxhde) . . . . . . . . . . . . . . . . . 44 table 25. port a?d stop mode recovery source enable subregisters (pxsmre) . . 45 table 26. port a?d pull-up enable subregisters (pxpue) . . . . . . . . . . . . . . . . . . . . 46 table 27. port a?d alternate function set 1 subreg isters (pxafs1) . . . . . . . . . . . . 47 table 28. port a?d alternate function set 2 subreg isters (pxafs2) . . . . . . . . . . . . 48
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xiii table 29. port a?c input data registers (pxin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 30. port a?d output data register (pxout) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. led drive enable (leden) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 32. led drive level high register (ledlvlh ) . . . . . . . . . . . . . . . . . . . . . . 51 table 33. led drive level low register (ledlvll) . . . . . . . . . . . . . . . . . . . . . . . 52 table 34. trap and interrupt vectors in order of prio rity . . . . . . . . . . . . . . . . . . . . . . 54 table 35. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 36. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 37. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. irq0 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 39. irq0 enable low bit register (irq0enl) . . . . . . . . . . . . . . . . . . . . . . . . 61 table 40. irq0 enable high bit register (irq0enh) . . . . . . . . . . . . . . . . . . . . . . . 61 table 41. irq1 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 42. irq1 enable high bit register (irq1enh) . . . . . . . . . . . . . . . . . . . . . . . 62 table 43. irq2 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 44. irq1 enable low bit register (irq1enl) . . . . . . . . . . . . . . . . . . . . . . . . 63 table 45. irq2 enable low bit register (irq2enl) . . . . . . . . . . . . . . . . . . . . . . . . 64 table 46. irq2 enable high bit register (irq2enh) . . . . . . . . . . . . . . . . . . . . . . . 64 table 47. interrupt edge select register (irqes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 48. shared interrupt select register (irqss) . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 49. interrupt control register (irqctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 50. timer 0?1 high byte register (txh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 51. timer 0?1 low byte register (txl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 52. timer 0?1 reload high byte register (t xrh) . . . . . . . . . . . . . . . . . . . . . . 85 table 53. timer 0?1 reload low byte register (txr l) . . . . . . . . . . . . . . . . . . . . . . 85 table 54. timer 0?1 pwm high byte register (txpwmh) . . . . . . . . . . . . . . . . . . . 86 table 55. timer 0?1 pwm low byte register (txpwml) . . . . . . . . . . . . . . . . . . . . 86 table 56. timer 0?1 control register 0 (txctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 57. timer 0?1 control register 1 (txctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 58. watchdog timer approximate time-out de lays . . . . . . . . . . . . . . . . . . . . 92
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xiv table 59. watchdog timer control register (wdtctl) . . . . . . . . . . . . . . . . . . . . . 95 table 60. watchdog timer reload upper byte register (wdtu) . . . . . . . . . . . . . . 96 table 61. watchdog timer reload high byte regi ster (wdth) . . . . . . . . . . . . . . . 96 table 62. watchdog timer reload low byte regist er (wdtl) . . . . . . . . . . . . . . . . 97 table 63. adc control register 0 (adcctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 64. adc data high byte register (adcd_h) . . . . . . . . . . . . . . . . . . . . . . . . 103 table 65. adc data low bits register (adcd_l) . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 66. sample settling time (adcsst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 67. sample time (adcst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 68. comparator control register (cmp0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 69. z8 encore! f0830 series flash memory configuration . . . . . . . . . . . . . . 108 table 70. z8f083 flash memory area map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 71. flash code protection using the flash option bits . . . . . . . . . . . . . . . . . . 115 table 72. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 73. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 74. flash page select register (fps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 75. flash sector protect register (fprot) . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 76. flash frequency high byte register ( ffreqh) . . . . . . . . . . . . . . . . . . . 123 table 77. flash frequency low byte register (ffr eql) . . . . . . . . . . . . . . . . . . . . 123 table 78. trim bit address register (trmadr) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 79. trim bit address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 80. trim bit data register (trmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 81. flash option bits at program memory address 0000h . . . . . . . . . . . . . . 127 table 82. flash options bits at program memory address 0001h . . . . . . . . . . . . . 128 table 83. trim option bits at 0000h (adcref) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 84. trim option bits at 0001h (tadc_comp) . . . . . . . . . . . . . . . . . . . . . . 130 table 85. trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 86. trim option bits at 0002h (tipo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 87. trim option bits at 0003h (tvbo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 88. vbo trim definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xv table 89. trim option bits at 0006h (tclkflt) . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 90. clkflt delay control definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 91. write status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 92. read status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 93. nvds read time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 94. ocd baud-rate limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 95. on-chip debugger command summary . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 96. ocd control register (ocdctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 97. ocd status register (ocdstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 98. oscillator configuration and selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 99. oscillator control register (oscctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 100. recommended crystal oscillator specific ations . . . . . . . . . . . . . . . . . . . 158 table 101. assembly language syntax example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 102. assembly language syntax example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 103. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 104. additional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 105. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 106. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 107. block transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 108. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 109. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 110. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 111. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 112. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 113. ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 114. op code map abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 115. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 116. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 117. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 118. power-on reset and voltage brown- out electrical characteristics and tim- ing 190
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xvi table 119. flash memory electrical characteristic s and timing . . . . . . . . . . . . . . . . 192 table 120. watchdog timer electrical characteri stics and timing . . . . . . . . . . . . . . 192 table 121. nonvolatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 122. analog-to-digital converter electrical characteristics and timing . . . . . 193 table 123. comparator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 124. gpio port input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 125. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 126. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 127. power consumption reference table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 128. z8 encore! xp f0830 series ordering ma trix . . . . . . . . . . . . . . . . . . . . . 200 table 129. package and pin count description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 130. timer 0 high byte register (t0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 131. timer 0 low byte register (t0l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 132. timer 0 reload high byte register (t0r h) . . . . . . . . . . . . . . . . . . . . . . . 209 table 133. timer 0 reload low byte register (t0rl) . . . . . . . . . . . . . . . . . . . . . . . 209 table 134. timer 0 pwm high byte register (t0pwmh) . . . . . . . . . . . . . . . . . . . . 209 table 135. timer 0 pwm low byte register (t0pwml) . . . . . . . . . . . . . . . . . . . . . 210 table 136. timer 0 control register 0 (t0ctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 137. timer 0 control register 1 (t0ctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 138. timer 1 high byte register (t1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 139. timer 1 low byte register (t1l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 140. timer 1 reload high byte register (t1r h) . . . . . . . . . . . . . . . . . . . . . . . 211 table 141. timer 1 reload low byte register (t1rl) . . . . . . . . . . . . . . . . . . . . . . . 211 table 142. timer 1 pwm high byte register (t1pwmh) . . . . . . . . . . . . . . . . . . . . 211 table 143. timer 1 pwm low byte register (t1pwml) . . . . . . . . . . . . . . . . . . . . . 212 table 144. timer 1 control register 0 (t1ctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 145. timer 1 control register 1 (t1ctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 146. adc control register 0 (adcctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 147. adc data high byte register (adcd_h) . . . . . . . . . . . . . . . . . . . . . . . . 214 table 148. adc data low bits register (adcd_l) . . . . . . . . . . . . . . . . . . . . . . . . . 214
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xvii table 149. adc sample settling time (adcsst) . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 150. adc sample time (adcst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 151. power control register 0 (pwrctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 152. led drive enable (leden) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 153. led drive level high register (ledlvlh ) . . . . . . . . . . . . . . . . . . . . . 217 table 154. led drive level low register (ledlvll) . . . . . . . . . . . . . . . . . . . . . . 217 table 155. oscillator control register (oscctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 156. comparator control register (cmp0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 157. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 158. irq0 enable high bit register (irq0enh) . . . . . . . . . . . . . . . . . . . . . . 219 table 159. irq0 enable low bit register (irq0enl) . . . . . . . . . . . . . . . . . . . . . . . 219 table 160. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 161. irq1 enable high bit register (irq1enh) . . . . . . . . . . . . . . . . . . . . . . 219 table 162. irq1 enable low bit register (irq1enl) . . . . . . . . . . . . . . . . . . . . . . . 220 table 163. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 164. irq2 enable high bit register (irq2enh) . . . . . . . . . . . . . . . . . . . . . . 220 table 165. irq2 enable low bit register (irq2enl) . . . . . . . . . . . . . . . . . . . . . . . 220 table 166. interrupt edge select register (irqes) . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 167. shared interrupt select register (irqss) . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 168. interrupt control register (irqctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 169. port a gpio address register (paaddr) . . . . . . . . . . . . . . . . . . . . . . . 222 table 170. port a control registers (pactl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 171. port a input data registers (pain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 172. port a output data register (paout) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 173. port b gpio address register (pbaddr) . . . . . . . . . . . . . . . . . . . . . . . 223 table 174. port b control registers (pbctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 175. port b input data registers (pbin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 176. port b output data register (pbout) . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 177. port c gpio address register (pcaddr) . . . . . . . . . . . . . . . . . . . . . . . 224 table 178. port c control registers (pcctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
ps025113-1212 list of tables z8 encore! ? f0830 series product specification xviii table 179. port c input data registers (pcin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 180. port c output data register (pcout) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 181. port d gpio address register (pdaddr) . . . . . . . . . . . . . . . . . . . . . . . 225 table 182. port d control registers (pdctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 183. port d output data register (pdout) . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 184. watchdog timer control register (wdtc tl) . . . . . . . . . . . . . . . . . . . . 226 table 185. reset status register (rststat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 186. watchdog timer reload upper byte re gister (wdtu) . . . . . . . . . . . . . 227 table 187. watchdog timer reload high byte re gister (wdth) . . . . . . . . . . . . . . 227 table 188. watchdog timer reload low byte regi ster (wdtl) . . . . . . . . . . . . . . . 227 table 189. trim bit address register (trmadr) . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 190. trim bit data register (trmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 191. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 192. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 193. flash page select register (fps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 194. flash sector protect register (fprot) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 195. flash frequency high byte register ( ffreqh) . . . . . . . . . . . . . . . . . . . 229 table 196. flash frequency low byte register (ffr eql) . . . . . . . . . . . . . . . . . . . . 230
ps025113-1212 overview z8 encore! ? f0830 series product specification 1 overview zilog?s z8 encore! mcu family of products ar e the first in a line of zilog microcontroller products based on the 8-bit ez8 cpu. the z8 encore! f0830 series products expand on zilog?s extensive line of 8-bit microcontrolle rs. the flash in-circuit programming capabil- ity allows for faster development time and program changes in the field. the new ez8 cpu is upward-compatible with existing z8 cp u instructions. the rich peripheral set of z8 encore! f0830 series makes it suitable fo r a variety of applica tions including motor control, security systems, home appliances, personal electronic devices and sensors. features the key features of z8 encore! f0830 series mcu include: ? 20 mhz ez8 cpu ? up to 12 kb flash memory with in-circuit programming capability ? up to 256 b register ram ? 64 b nonvolatile data storage (nvds) ? up to 25 i/o pins depending upon package ? internal precision oscillator (ipo) ? external crystal oscillator ? two enhanced 16-bit timers with capture, compare and pwm capability ? watchdog timer (wdt) with de dicated internal rc oscillator ? single-pin, on-chip debugger (ocd) ? optional 8-channel, 10-bit anal og-to-digital converter (adc) ? on-chip analog comparator ? up to 17 interrupt sources ? voltage brown-out (vbo) protection ? power-on reset (por) ? 2.7 v to 3.6 v operating voltage ? up to thirteen 5 v-tolerant input pins ? 20- and 28-pin packages ? 0c to +70c standard temperature range an d ?40c to +105c extended temperature operating ranges
ps025113-1212 part selection guide z8 encore! ? f0830 series product specification 2 part selection guide table 1 lists the basic features available fo r each device within the z8 encore! f0830 series product line. see the ordering information chapter on page 200 for details. table 1. z8 encore! f0830 series family part selection guide part number flash (kb) ram (b) nvds (64b) adc z8f1232 12 256 no yes z8f1233 12 256 no no z8f0830 8 256 yes yes z8f0831 8 256 yes no z8f0430 4 256 yes yes z8f0431 4 256 yes no Z8F0230 2 256 yes yes z8f0231 2 256 yes no z8f0130 1 256 yes yes z8f0131 1 256 yes no
ps025113-1212 block diagram z8 encore! ? f0830 series product specification 3 block diagram figure 1 displays a block diagram of the z8 encore! f0830 series architecture . figure 1. z8 encore! f0830 series block diagram gpio timers adc flash controller ram ram controller interrupt controller on-chip debugger ez8 cpu wdt por/vbo & reset controller xtal/rc oscillator register bus memory bus system clock comparator nvds controller low power rc oscillator internal oscillator control oscillator precision flash memory
ps025113-1212 cpu and peripheral overview z8 encore! ? f0830 series product specification 4 cpu and peripheral overview the ez8 cpu, zilog?s latest 8-bit cpu, meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cp u executes a superset of the original z8 instruction set. the ez8 cpu features include: ? direct register-to-register architecture allows each register to fu nction as an accumula- tor, improving execution time and decreasing the required program memory ? software stack allows much greater depth in subroutine calls and interrupts than hard- ware stacks ? compatible with ex isting z8 cpu code ? expanded internal register file allows access up to 4 kb ? new instructions improve execution efficien cy for code developed using high-level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c compiler-friendly ? 2 to 9 clock cycles per instruction ? for more information about the ez8 cpu, refer to the ez8 cpu core user manual (um0128) , which is available for download on www.zilog.com . general purpose input/output the z8 encore! f083 0 series features up to 25 port pins (ports a?d) for general-purpose input/output (gpio). the number of gpio pins available is a function of package. each pin is individually programmable. flash controller the flash controller programs and erases the flash memory. it also supports protection against accidental programming and erasure.
ps025113-1212 cpu and peripheral overview z8 encore! ? f0830 series product specification 5 nonvolatile data storage the nonvolatile data storage (nvds) functio n uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of storing about 100,000 write cycles. internal precision oscillator the internal precision oscillator (ipo) func tion, with an accuracy of 4% full voltage/ temperature range, is a trimmable clock so urce that requires no external components. external crystal oscillator the crystal oscillator circuit pr ovides highly accurate clock fre quencies using an external crystal, ceramic resonator or rc network. 10-bit analog-to- digital converter the optional analog-to-digital converter (adc) converts an analog in put signal to a 10- bit binary number. the adc accepts inputs from eight different analog input pins. analog comparator the analog comparator compares the signal at an input pin with either an internal pro- grammable reference voltage or with a signal at the second input pin. the comparator out- put is used either to drive a logic ou tput pin or to generate an interrupt. timers two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provid e a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, capture restart, compare, capture and compare, pwm single output and pwm dual output modes. interrupt controller the z8 encore! f0830 series products suppor t seventeen interrupt sources with sixteen interrupt vectors: up to five internal periph eral interrupts and up to twelve gpio inter- rupts. these interrupts have three leve ls of programmable interrupt priority.
ps025113-1212 acronyms and expansions z8 encore! ? f0830 series product specification 6 reset controller the z8 encore! f0830 series products are r eset using any one of the following: the reset pin, power-on reset, watchdog timer (wdt) time-out, stop mode exit or volt- age brown-out (vbo) warning signal. the reset pin is bidirectional; i.e., it functions as a reset source as well as a reset indicator. on-chip debugger the z8 encore! f0830 series products featur e an integrated on-chip debugger (ocd). the ocd provides a rich set of debugging capabilities, such as re ading and writing regis- ters, programming flash memory, setting break points and executing code. the ocd uses one single-pin interface for commun ication with an external host. acronyms and expansions this document references a number of acronyms; each is expanded in table 2 for the reader?s understanding. table 2. acronyms and expansions acronyms expansions adc analog-to-digital converter nvds nonvolatile data storage wdt watchdog timer gpio general-purpose input/output ocd on-chip debugger por power-on reset vbo voltage brown-out ipo internal precision oscillator pdip plastic dual inline package soic small outline integrated circuit ssop small shrink outline package qfn quad flat no lead irq interrupt request isr interrupt service routine msb most significant byte lsb least significant byte pwm pulse width modulation sar successive approximation regis-
ps025113-1212 pin description z8 encore! ? f0830 series product specification 7 pin description the z8 encore! f0830 series pr oducts are available in a vari ety of package styles and pin configurations. this chapter d escribes the signals and the pin configurations for each of the package styles. for information about th e physical package specifications, see the packaging chapter on page 199. available packages table 3 lists the package styles that are available for each device in the z8 encore! f0830 series product line. pin configurations figures 2 and 3 display the pin configurations of all of the packages available in the z8 encore! f0830 series. see table 4 on page 11 for a descrip tion of the signals. analog input alternate functions (anax) are not available on the following devices: ? z8f0831 ? z8f0431 ? z8f0131 ? z8f0231 ? z8f1233 table 3. z8 encore! f0830 series package options part number adc 20-pin qfn 20-pin soic 20-pin ssop 20-pin pdip 28-pin qfn 28-pin soic 28-pin ssop 28-pin pdip z8f1232yesxxxxxxxx z8f1233noxxxxxxxx z8f0830yesxxxxxxxx z8f0831noxxxxxxxx z8f0430yesxxxxxxxx z8f0431noxxxxxxxx Z8F0230yesxxxxxxxx z8f0231noxxxxxxxx z8f0130yesxxxxxxxx z8f0131noxxxxxxxx
ps025113-1212 pin configurations z8 encore! ? f0830 series product specification 8 the analog supply pins (av dd and av ss ) are also not available on these parts and are replaced by pb6 and pb7. at reset, by default, all pins of port a, b an d c are in input state. the alternate functional- ity is also disabled, so the pins function as general purpose input ports until programmed otherwise. at power- up, the port d0 pin defaults to the reset alternate function. the pin configurations listed are preliminary and subject to change based on manufactur- ing limitations. figure 2. z8f0830 series in 20-pin soic, ssop, pdip package figure 3. z8f0830 series in 28-pin soic, ssop, pdip package pb0/ana0 pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pa7/t1out pa6/t1in/t1out pb1/ana1 pb2/ana2 pb3/clkin/ana3 v dd pa0/t0in/t0out /x in pa1/t0out/xout v ss pa2 1 pa5 pa3 5 10 pa4 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb1/ana1 pb0/ana0 pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pc7/led pb2/ana2 pb3/clkin/ana3 pb4/ana7 pb5/v ref (pb6) av dd v dd pa0/t0in/t0out /x in pa1/t0out/x out 1 pc6/led v ss 5 10 (pb7) av ss pa2 pa3 pa4 14 pa5 2 3 4 6 7 8 9 11 12 13 pc5/led pc4/led pa7/t1out pa6/t1in/t1out 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps025113-1212 pin configurations z8 encore! ? f0830 series product specification 9 figure 4. z8f0830 series in 20-pin qfn package 16 17 18 19 20 pc3/cout/led pb0/ana0 pb1/ana1 pb2/ana2 pb3/clkin/ana3 pa7/t1out ? pa6/t1in/t1out ? ? pa5 ? ? pa4 ? ? pa3 vdd pa0/t0in/t0out /xin pa1/t0out/xout vss pa2 pc2/ana6/led ? pc1/ana5/cinn/led ? pc0/ana4/cinp/led ? dgb ? reset /pd0 20-pin qfn 10 9 8 7 6 1 2 3 4 5 15 14 13 12 11 pa7/t1out ? pa6/t1in/t1out ? ? pa5 ? ? pa4 ? ? pa3
ps025113-1212 pin configurations z8 encore! ? f0830 series product specification 10 figure 5. z8f0830 series in 28-pin qfn package (pb6) avdd vdd pa0/t0in/t0out /xin pa1/t0out/xout vss (pb7) avss pa2 pc2/ana6/led ? pc1/ana5/cinn/led ? pc0/ana4/cinp/led ? dbg reset /pd0 pc7/led ? pc6/led 15 21 28-pin qfn pa7/t1out 14 13 12 11 10 9 pc5/led pc4/led pa6/t1in/t1out pa5 pa4 pa3 22 23 24 25 26 27 pb0/ana0 pb1/ana1 pb5/ v ref pc3/cout/led pb2/ana2 pb4/ana7 pb3/clkin/ana3 20 16 17 1819 7 12 6543
ps025113-1212 signal descriptions z8 encore! ? f0830 series product specification 11 signal descriptions table 4 describes the z8 encore! f0830 series signals. see the pin configurations section on page 7 to determine the signals ava ilable for each specific package style. table 4. signal descriptions signal mnemonic i/o description general-purpose i/o ports a?d pa[7:0] i/o port a. these pins are used for general purpose i/o. pb[7:0] i/o port b. these pins are used for general purpose i/o. pb6 and pb7 are available only in those devices without an adc. pc[7:0] i/o port c. these pins are used for general purpose i/o. pd[0] i/o port d. this pin is used for general purpose output only. note: pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are re- placed by av dd and av ss . timers t0out/t1out o timer output 0?1. these signa ls are the output from the timers. t0out /t1out o timer complement output 0?1. these signals are output from the timers in pwm dual output mode. t0in/t1in i timer input 0?1. these signals ar e used as the capture, gating and counter inputs. the t0in signal is multiplexed t0out signals. comparator cinp/cinn i comparator inputs. these signals are the positive and negative inputs to the comparator. cout o comparator output. this is the output of the comparator. analog ana[7:0] i analog port. these signals are used as inputs to the analog-to-digital con- verter (adc). v ref i/o analog-to-digital converter reference voltage input. ? note: when configuring adc using external v ref , pb5 is used as v ref in 28-pin package. note: the av dd and av ss signals are available only in the 28-pin pa ckages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc.
ps025113-1212 signal descriptions z8 encore! ? f0830 series product specification 12 oscillators x in i external crystal input. this is the input pin to the crystal oscillator. a crystal can be connected between it and the xout pin to form the oscillator. in addition, this pin is used with external rc networks or external clock drivers to provide the system clock. x out o external crystal output. this pin is th e output of the crystal oscillator. a crys- tal can be connected between it and the xin pin to form the oscillator. clock input clk in i clock input signal. this pin may be used to input a ttl-level signal to be used as the system clock. led drivers led o direct led drive capability. all port c pins have the capability to drive an led without any other external comp onents. these pins have programma- ble drive strengths set by the gpio block. on-chip debugger dbg i/o debug. this signal is the control and data input and output to and from the on-chip debugger. ? caution: the dbg pin is open-drain and requires an external pull-up resis- tor to ensure proper operation. reset reset i/o reset. generates a reset when asserted (driven low). also serves as a reset indicator; the z8 encore! forces th is pin low when in reset. this pin is open-drain and features an enab led internal pull-up resistor. power supply v dd i digital power supply. av dd i analog power supply. v ss i digital ground. av ss i analog ground. table 4. signal descriptions (continued) signal mnemonic i/o description note: the av dd and av ss signals are available only in the 28-pin pa ckages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc.
ps025113-1212 pin characteristics z8 encore! ? f0830 series product specification 13 pin characteristics table 5 provides detailed characteristics of each pin available on the z8 encore! f0830 series 20- and 28-pin devices. data in table 5 are sorted alphabetically by the pin symbol mnemonic. pb6 and pb7 are available only in devices without an adc function. table 5. pin characteristic s (20- and 28-pin devices) symbol ? mnemonic direction reset direction active low or active high tristate output internal pull-up or pull-down schmitt- trigger input open drain output 5 v tolerance av dd n/a n/a n/a n/a n/a n/a n/a n/a av ss n/a n/a n/a n/a n/a n/a n/a na dbg i/o i n/a yes no yes yes yes pa[7:0] i/o i n/a yes programma- ble pull-up yes yes, programma- ble pa[7:2] only pb[7:0] i/o i n/a yes programma- ble pull-up yes yes, programma- ble pb[7:6] only pc[7:0] i/o i n/a yes programma- ble pull-up yes yes, programma- ble pc[7:3] only reset/pd0 i/o i/o (defaults to reset ) low (in reset mode) yes (pd0 only) programma- ble for pd0; always on for reset yes programma- ble for pd0; always on for reset yes v dd n/a n/a n/a n/a n/a n/a v ss n/a n/a n/a n/a n/a n/a note:
ps025113-1212 address space z8 encore! ? f0830 series product specification 14 address space the ez8 cpu can access the following three distinct address spaces: ? the register file addresses access for the ge neral purpose registers and the ez8 cpu, peripheral and general purpose i/o port control registers ? the program memory addresses access for all of the memory locations having execut- able code and/or data ? the data memory addresses access for all of the memory locations containing only the data ? the following sections describe these three address spaces. for more information about the ez8 cpu and its address space, refer to the ez8 cpu core user manual (um0128) , which is available for download at www.zilog.com . register file the register file address space in the z8 encore! mcu is 4 kb (4096 bytes). the register file consists of two sections : control registers and general-purpose registers. when instruc- tions are executed, registers defined as source are read and registers defined as destina- tions are written. the architecture of the ez8 cp u allows all general purpose registers to function as accumulators, address pointers, index registers, stack areas or scratch pad memory. the upper 256 bytes of the 4 kb register file address space are reserved for controlling the ez8 cpu, on-chip peripherals and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256 b control register section are reserved (unavailable). reading from a reserved register file address returns an undefined value. writing to reserved register file addresses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. the z8 encore! f0830 series devices contain up to 25 6 b of on-chip ram. reading from register file addresses outside the available ram addr esses (and not within the control register address space), returns an undefined value. writ ing to these register file addresses has no effect.
ps025113-1212 program memory z8 encore! ? f0830 series product specification 15 program memory the ez8 cpu supports 64 kb of program memory address space. the z8 encore! f0830 series devices contain 1 kb to 12 kb of on -chip flash memory in the program memory address space, depending on the device. read ing from program memory addresses outside the available flash memory address range returns ffh . writing to these unimplemented program memory addresses produces no effect . table 6 shows a program memory map for the z8 encore! f0830 series products. table 6. z8 encore! f0830 series program memory maps program memory address (hex) function z8f0830 and z8f0831 products 0000?0001 flash option bits 0002?0003 reset vector 0004?003d interrupt vectors* 003e?1fff program memory z8f0430 and z8f0431 products 0000?0001 flash option bits 0002?0003 reset vector 0004?003d interrupt vectors* 003e?0fff program memory z8f0130 and z8f0131 products 0000?0001 flash option bits 0002?0003 reset vector 0004?003d interrupt vectors* 003e?03ff program memory Z8F0230 and z8f0231 products 0000?0001 flash option bits 0002?0003 reset vector 0004?003d interrupt vectors* 003e?07ff program memory note: *see table 34 on page 54 for a list of interrupt vectors.
ps025113-1212 data memory z8 encore! ? f0830 series product specification 16 data memory the z8 encore! f0830 series does not use th e ez8 cpu?s 64 kb data memory address space. flash information area table 7 maps the z8 encore! f0830 series fl ash information area. the 128-byte informa- tion area is accessed, by setting bit 7 of the flas h page select register to 1. when access is enabled, the flash information area is mapped into program memory and overlays these 128 bytes at addresses fe00h to fe7fh . when information area access is enabled, all reads from these program memory addresses retu rn information area data rather than pro- gram memory data. access to the fl ash information area is read-only. table 7. z8 encore! f0830 series flash memory information area map program memory address (hex) function fe00?fe3f zilog option bits fe40?fe53 part number 20-character ascii alphanumeric code left-justified and filled with fh fe54?fe5f reserved fe60?fe7f reserved fe80?ffff reserved
ps025113-1212 register map z8 encore! ? f0830 series product specification 17 register map table 8 provides an address map of the z8 en core! f0830 series register file. not all devices and package styl es in the z8 encore! f0830 seri es support the adc or all of the gpio ports. consider registers for unimplemented peripherals as reserved. table 8. register file address map address (hex) register description mnemonic reset (hex) page no. general purpose ram 000?0ff general purpose register file ram ? xx 100?eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 83 f01 timer 0 low byte t0l 01 83 f02 timer 0 reload high byte t0rh ff 85 f03 timer 0 reload low byte t0rl ff 85 f04 timer 0 pwm high byte t0pwmh 00 86 f05 timer 0 pwm low byte t0pwml 00 86 f06 timer 0 control 0 t0ctl0 00 87 f07 timer 0 control 1 t0ctl1 00 88 timer 1 f08 timer 1 high byte t1h 00 83 f09 timer 1 low byte t1l 01 83 f0a timer 1 reload high byte t1rh ff 85 f0b timer 1 reload low byte t1rl ff 85 f0c timer 1 pwm high byte t1pwmh 00 86 f0d timer 1 pwm low byte t1pwml 00 86 f0e timer 1 control 0 t1ctl0 00 87 f0f timer 1 control 1 t1ctl1 00 83 f10?f6f reserved ? xx analog-to-digital converter (adc) f70 adc control 0 adcctl0 00 102 f71 reserved ? xx f72 adc data high byte adcd_h xx 103 note: xx = undefined.
ps025113-1212 register map z8 encore! ? f0830 series product specification 18 analog-to-digital converter (adc, cont?d) f73 adc data low bits adcd_l xx 103 f74 adc sample settling time adcsst 0f 104 f75 adc sample time adcst 3f 105 f76 reserved ? xx f77?f7f reserved ? xx low power control f80 power control 0 pwrctl0 88 32 f81 reserved ? xx led controller f82 led drive enable leden 00 51 f83 led drive level high ledlvlh 00 51 f84 led drive level low ledlvll 00 52 f85 reserved ? xx oscillator control f86 oscillator control oscctl a0 154 f87?f8f reserved ? xx comparator 0 f90 comparator 0 control cmp0 14 107 f91?fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 58 fc1 irq0 enable high bit irq0enh 00 61 fc2 irq0 enable low bit irq0enl 00 61 fc3 interrupt request 1 irq1 00 59 fc4 irq1 enable high bit irq1enh 00 62 fc5 irq1 enable low bit irq1enl 00 63 fc6 interrupt request 2 irq2 00 60 fc7 irq2 enable high bit irq2enh 00 64 fc8 irq2 enable low bit irq2enl 00 64 fc9?fcc reserved ? xx fcd interrupt edge select irqes 00 66 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps025113-1212 register map z8 encore! ? f0830 series product specification 19 interrupt controller (cont?d) fce shared interrupt select irqss 00 66 fcf interrupt control irqctl 00 67 gpio port a fd0 port a address paaddr 00 39 fd1 port a control pactl 00 41 fd2 port a input data pain xx 41 fd3 port a output data paout 00 41 gpio port b fd4 port b address pbaddr 00 39 fd5 port b control pbctl 00 41 fd6 port b input data pbin xx 41 fd7 port b output data pbout 00 41 gpio port c fd8 port c address pcaddr 00 39 fd9 port c control pcctl 00 41 fda port c input data pcin xx 41 fdb port c output data pcout 00 41 gpio port d fdc port d address pdaddr 00 39 fdd port d control pdctl 00 41 fde reserved ? xx fdf port d output data pdout 00 41 fe0?fef reserved ? xx watchdog timer (wdt) ff0 reset status rststat xx 95 watchdog timer control wdtctl xx 95 ff1 watchdog timer reload upper byte wdtu ff 96 ff2 watchdog timer reload high byte wdth ff 96 ff3 watchdog timer reload low byte wdtl ff 97 ff4?ff5 reserved ? xx table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps025113-1212 register map z8 encore! ? f0830 series product specification 20 trim bit control ff6 trim bit address trmadr 00 126 ff7 trim data trmdr xx 127 flash memory controller ff8 flash control fctl 00 119 ff8 flash status fstat 00 120 ff9 flash page select fps 00 121 flash sector protect fprot 00 122 ffa flash programming frequency high byte ffreqh 00 123 ffb flash programming frequency low byte ffreql 00 123 ez8 cpu ffc flags ? xx refer to the ez8 cpu core user manual (um0128) ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no. note: xx = undefined.
ps025113-1212 reset and stop mode recovery z8 encore! ? f0830 series product specification 21 reset and stop mode recovery the reset controller in the z8 encore! f0 830 series controls reset and stop mode recovery operations. in a ty pical operation, the follow ing events can cause a reset: ? power-on reset (por) ? voltage brown-out (vbo) ? watchdog timer time-out (when configured by the wdt_res flash option bit to initiate a reset) ? external reset pin assertion (when the alternate reset function is enabled by the gpio register) ? on-chip debugger initiated re set (ocdctl[0] set to 1) ? when the device is in stop mode, a stop m ode recovery event is initiated by either of the following occurrences: ? a watchdog timer time-out ? a gpio port input pin transition on an enabled stop mode recovery source ? the vbo circuitry on the device generates a vbo reset when the supply voltage drops below a minimum safe level. reset types the z8 encore! f0830 series provides differ ent types of reset operations. stop mode recovery is considered a form of reset. table 9 lists the types of resets and their operating characteristics. the duration of a system reset is longer if the external crystal oscillator is enabled by the flash option bits; the result is additional time for oscillator startup.
ps025113-1212 reset types z8 encore! ? f0830 series product specification 22 during a system reset or stop mode recovery, the z8 enco re! f0830 series device is held in reset for about 66 cycles of the internal precision oscillator. if the crystal oscillator is enabled in the flash option b its, the reset period is increas ed to about 5000 ipo cycles. when a reset occurs because of a low voltage condition or power-on reset, the reset delay is measured from the time that the supply vo ltage first exceeds the por level (discussed later in this chapter). if the external pin r eset remains asserted at the end of the reset period, the device re mains in reset until the pin is deasserted. at the beginning of reset, all gpio pins are co nfigured as inputs with pull-up resistor dis- abled, except pd0 which is shared with the rese t pin. on reset, the port d0 pin is config- ured as a bidirectional open-drain reset. this pin is internally driven lo w during port reset, after which the user code may reconfigur e this pin as a general purpose output. during reset, the ez8 cpu and on-chip peripherals are idle; however, the on-chip crystal oscillator and watchdog timer oscillator continues to run. on reset, control registers within the register f ile that have a defined reset value are loaded with their reset values. other control regist ers (including the stack pointer, register pointer and flags) and general purpose ram are undefined following the reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. program execution begins at the reset vector address. because the control registers are reinitialized by a system reset, the system clock after reset is always the ipo. user software must reconfigure the oscillator control block, to enable and select the corr ect system clock source. table 9. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as applicable) reset a bout 66 internal pr ecision oscillator cycles system reset with crystal oscillator enabled reset (as applicable) reset about 5000 internal precision oscillator cycles stop mode recovery unaffected, except wdt_ctl and osc_ctl registers reset about 66 in ternal precision oscillator cycles stop mode recovery with crystal oscillator enabled unaffected, except wdt_ctl and osc_ctl registers reset about 5000 in ternal precision oscillator cycles
ps025113-1212 reset sources z8 encore! ? f0830 series product specification 23 reset sources table 10 lists the possible sources of a system reset. power-on reset each device in the z8 encore! f0830 series co ntains an internal power-on reset circuit. the por circuit monitors the digital supply vo ltage and holds the device in the reset state until the digital supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the device is held in the reset state until the por counter has timed out. if the crystal oscilla tor is enabled by the option bits, the time- out is longer. after the z8 encore! f0830 series device exits the power-on reset state, the ez8 cpu fetches the reset vector. following the power- on reset, the por status bit in the reset status (rststat) register is set to 1. figure 6 displays the power- on reset operation. see the electrical characteristics chapter on page 184 for the por threshold voltage (v por ). table 10. reset sources and resulting reset type operating mode reset source special conditions normal or halt modes power-on reset/voltage brown-out reset delay begins after supply voltage exceeds por level. watchdog timer time-out when con- figured for reset none. reset pin assertion all reset pulses less than four system clocks in width are ignored. on-chip debugger initiated reset (ocdctl[0] set to 1) system, except the on-chip debugger is unaffected by the reset. stop mode power-on reset/voltage brown-out reset delay begins after supply voltage exceeds por level. reset pin assertion all reset pulses less than 12 ns are ignored. dbg pin driven low none.
ps025113-1212 reset sources z8 encore! ? f0830 series product specification 24 voltage brown-out reset the devices in the z8 encore! f0830 series provide low voltage brown-out (vbo) pro- tection. the vbo circuit forces the device to the reset state, when the supply voltage drops below the vbo threshold voltage (unsafe level). while the supply voltage remains below the power-on reset threshold voltage (v por ), the vbo circuit holds the device in reset. after the supply voltage exc eeds the power-on reset threshold voltage, the device pro- gresses through a full system reset sequence, as described in the por section. following power-on reset, the por status bit in the re set status (rststat) register is set to 1. figure 7 displays the voltage brown-out operation. see the electrical characteristics chapter on page 184 for the vbo and por threshold voltages (v vbo and v por ). the por level is greater than the vbo leve l by the specified hysteresis value. this ensures that the device undergoes a po r after recovering from a vbo condition. figure 6. power-on reset operation vdd = 0.0v vdd = 3.3v v por v vbo internal precision internal reset signal program execution oscillator start-up por counter delay optional xtal counter delay oscillator crystal oscillator note: not to scale
ps025113-1212 reset sources z8 encore! ? f0830 series product specification 25 the voltage brown-out circuit can be either enabled or disabled during stop mode. operations during stop mode is set by the vbo_ao flash option bit. see the flash option bits chapter on page 124 for information about configuring vbo_ao. watchdog timer reset if the device is operating in normal or stop mode, the watchdog timer can initiate a system reset at time-out if the wdt_res flash opt ion bit is programmed to 1; this state is the unprogrammed state of the wdt_res flash option bit. if the bit is programmed to 0, it configures the watchdog timer to cause an interrupt ? not a system reset ? at time-out. the wdt status bit in the reset status (rststat) register is set to 1 to signify that the reset was initiated by the watchdog timer. external reset input the reset pin has a schmitt-triggered input and an internal pull-up resistor. after the reset pin is asserted for a minimum of four sy stem clock cycles, th e device progresses through the system reset sequence. because of the possible asynchronicity of the system figure 7. voltage brown-out reset operation v dd = 3.3v v por v vbo internal reset signal program execution program execution voltage brown-out v dd = 3.3v system clock wdt clock por counter delay note: not to scale
ps025113-1212 stop mode recovery z8 encore! ? f0830 series product specification 26 clock and reset signals, the required reset dura tion may be three or four clock periods. a reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four cycles in duration always triggers a reset. while the reset input pin is asserted low, the z8 encore! f0830 series devices remain in the reset state. if the reset pin is held low beyond th e system reset time-out, the device exits the reset state on the sy stem clock rising edge following reset pin deasser- tion. following a system reset initiated by the external reset pin, the ext status bit in the reset status (rststat) register is set to 1. external reset indicator during system reset or when enab led by the gpio logic, the reset pin functions as an open-drain (active low) reset mode indicator in addition to the in put functionality. this reset output feature allows an z8 encore! f0 830 series device to re set other components to which it is connected, even if that reset is caused by inte rnal sources such as por, vbo or wdt events. see the port a?d control registers section on page 41. after an internal reset event occurs, the internal circuitry begins driving the reset pin low. the reset pin is held low by the internal ci rcuitry until the appropriate delay listed in table 9 (see page 22) has elapsed. on-chip debugger initiated reset a power-on reset can be initiated usi ng the on-chip debugger by setting the rst bit in the ocd control register. the ocd block is no t reset, but the remainder of the chip goes through a normal system reset. the rst bit automatically clears during the system reset. following the system reset, the por bit in the reset status (rststat) register is set. stop mode recovery the device enters the stop mode when the stop instruction is executed by the ez8 cpu. see the low-power modes chapter on page 30 for detailed stop mode informa- tion. during stop mode recovery, the cpu is he ld in reset for about 66 ipo cycles if the crystal oscillator is disabled or ab out 5000 cycles if it is enabled. stop mode recovery does not affect the on-chip registers other than the reset status (rststat) register and the oscillator cont rol register (oscctl). after any stop mode recovery, the ipo is enabled and selected as the system clock. if another system clock source is required or ipo disabling is required, the stop mode recovery code must reconfigure the oscillator cont rol block such that the correct system clock source is enabled and selected.
ps025113-1212 stop mode recovery z8 encore! ? f0830 series product specification 27 the ez8 cpu fetches the reset vect or at program memory addresses 0002h and 0003h and loads that value into the program counter. program execution begins at the reset vector address. following stop mode recovery, the stop bit in the reset status (rststat) register is set to 1. table 11 lists the st op mode recovery sour ces and resulting actions. the following sections provid e more details about each of the stop mode recovery sources. stop mode recovery using wdt time-out if the watchdog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the reset status (rststat) register, the wdt and stop bits are set to 1. if the watchdog timer is configured to generate an interrupt upon time-out and the z8 encore! f0830 series device is configured to respond to interrupts, the ez8 cpu services the wdt interrupt request following the normal stop mode recovery sequence. stop mode recovery using gpio port pin transition each of the gpio port pins may be configured as a stop mode recovery input source. if any gpio pin is enabled as a stop mode recove ry source, a change in the input pin value (from high to low or from low to high) initia tes stop mode recovery. in the reset sta- tus (rststat) register, the stop bit is set to 1. in stop mode, the gpio port input data regi sters (pxin) are disabled. these port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. as a r esult, short pulses on the port pin can initiate stop mode recovery without being written to th e port input data regi ster or without ini- tiating an interrupt (if enabled for that pin). table 11. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watchdog timer time-out when configured for reset stop mode recovery watchdog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery assertion of external reset pin system reset debug pin driven low system reset caution:
ps025113-1212 debug pin driven low z8 encore! ? f0830 series product specification 28 stop mode recovery using the external reset pin when the z8 encore! f0830 series device is in stop mode and the external reset pin is driven low, a system reset occurs. becaus e of a glitch filter operating on the reset pin, the low pulse must be greate r than the minimum width spec ified about 12 ns or it is ignored. the ext bit in the reset status (rststat) register is set. debug pin driven low debug reset is initiated when the on-chip debugger detects any of the following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (simultaneou s ocd and host transmissi on detected by the ocd) ? when the z8f0830 series device is operating in stop mode, the debug reset will cause a system reset. the on-chip debugger block is not reset, but the remainder of the chip?s operations go through a normal system rese t. the por bit in the reset status (rststat) register is set to 1. reset register definitions the following sections de fine the reset registers. reset status register the reset status (rststat) register, shown in table 12, is a read-only register that indi- cates the source of the most recent reset event, stop mode recovery event or watchdog timer time-out event. readi ng this register resets th e upper four bits to 0. this register shares its address with the watc hdog timer control register, which is write- only.
ps025113-1212 reset register definitions z8 encore! ? f0830 series product specification 29 table 12. reset status register (rststat) bit 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset see table 13 00000 r/w rrrrrrrr address ff0h bit description [7] ? por power-on reset indicator this bit is set to 1 if a power-on reset event occu rs and is reset to 0, if a wdt time-out or stop mode recovery occu rs. reading this register also reset this bit to 0. [6] ? stop stop mode recovery indicator this bit is set to 1 if a stop mode recovery occurs. if the stop and wdt bits are both set to 1, the stop mode recovery occurs because of a wd t time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery is not caused by a wdt time-out. this bi t is reset by a power- on reset or a wdt time-out that occurred while not in stop mode. reading this register also resets this bit. [5] ? wdt watchdog timer time-out indicator this bit is set to 1 if a wdt time-out occurs. a power-on reset resets this pin. a stop mode recovery from a change in an input pin also resets this bit. reading this register resets this bit. this read must occur before clearing the wdt interrupt. [4] ? ext external reset indicator if this bit is set to 1, a rese t initiated by t he external reset pin occurred. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. [3:0] reserved these registers are reserved and must be programmed to 0000. table 13. por indicator values reset or stop mode recovery event por stop wdt ext power-on reset 1000 reset using reset pin assertion 0001 reset using watchdog timer time-out 0010 reset using the on-chip debugger (octctl[1] set to 1) 1000 reset from stop mode using dbg pin driven low 1000 stop mode recovery using gpio pin transition 0100 stop mode recovery using wdt time-out 0110
ps025113-1212 low-power modes z8 encore! ? f0830 series product specification 30 low-power modes the z8 encore! f0830 series products contain power saving features. the highest level of power reduction is provided by the stop mode . the next level of power reduction is pro- vided by the halt mode. further power savings can be implemented by disabling the individual peripheral blocks while in normal mode. the user must not enable the pu ll-up register bits for unused gpio pins, since these ports are default output to vss. unused gpios in clude those missing on 20-pin packages, as well as those missing on the adc-enabled 28-pin packages. stop mode executing the ez8 cpu?s stop instruction pl aces the device into stop mode. in stop mode, the operating characteristics are: ? primary crystal oscillator and internal precision oscillator are stopped; xin and xout (if previously enabled) are disabled and pa0/pa1 revert to the states pro- grammed by the gpio registers ? system clock is stopped ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watchdog timer?s internal rc oscillator co ntinues to operate if enabled by the oscil- lator control register ? if enabled, the watchdog time r logic continues to operate ? if enabled for operation in stop mode by th e associated flash option bit, the voltage brown-out protection circuit continues to operate ? all other on-chip peripherals are idle ? to minimize the current in stop mode, all gpio pins that are configured as digital inputs must be driven to v dd when the pull-up register bit is enabled or to one of power rail (v dd or gnd) when the pull-up register bit is disabled. the device can be brought out of stop mode using stop mode recovery. for more information abou t stop mode recov- ery, see the reset and stop mode recovery chapter on page 21 .
ps025113-1212 halt mode z8 encore! ? f0830 series product specification 31 halt mode executing the ez8 cpu halt instruction places the device into halt mode. in halt mode, the operating characteristics are: ? primary oscillator is enable d and continues to operate ? system clock is enabled and continues to operate ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watchdog timer?s internal rc oscillator continues to operate ? if enabled, the watchdog ti mer continues to operate ? all other on-chip peripherals continue to operate ? the ez8 cpu can be brought out of halt mode by any one of the following operations: ? interrupt ? watchdog timer time-out (interrupt or reset) ? power-on reset ? voltage brown-out reset ? external reset pin assertion ? to minimize current in halt mode, all gpio pins that are configured as digital inputs must be driven to v dd when pull-up register bit is en abled or to one of power rail (v dd or gnd) when pull-up register bit is disabled. peripheral level power control in addition to the stop and halt modes, it is possible to disable each peripheral on each of the z8 encore! f0830 series devices. disab ling a given peripheral minimizes its power consumption. power control register definitions power control register 0 each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block.
ps025113-1212 power control register definitions z8 encore! ? f0830 series product specification 32 this register is only reset during a power-on reset sequence. other system reset events do not affect it. table 14. power control register 0 (pwrctl0) bit 7 6 5 4 3 2 1 0 field reserved vbo reserved re served comp reserved reset 10001000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f80h bit description [7:5] reserved these registers are reserved and must be programmed to 000. [4] ? vbo voltage brown-out detector disable this bit takes only effect when the vbo_ao fl ash option bit is disabled. in stop mode, vbo is always disabled when the vbo_ao flash option bit is disabled. to learn more about the vbo_ao flash option bit function, see the flash option bits chapter on page 124. 0 = vbo enabled. 1 = vbo disabled. [3] reserved this bit is reserved and must be programmed to 1. [2] reserved this bit is reserved and must be programmed to 0. [1] ? comp comparator disable 0 = comparator is enabled. 1 = comparator is disabled. [0] reserved this bit is reserved and must be programmed to 0. note:
ps025113-1212 general purpose input/output z8 encore! ? f0830 series product specification 33 general purpose input/output the z8 encore! f0830 series products support a maximum of 25 port pins (ports a?d) for general purpose input/output (gpio) operations. each port contains control and data registers. the gpio control registers determin e data direction, open-drain, output drive current, programmable pull-ups, stop mode recovery functionality and alternate pin functions. each port pin is individually programmable. in addition, the port c pins are capable of direct led drive at programmable drive strengths. gpio port availability by device table 15 lists the port pins availa ble with each device and package type. table 15. port availability by device and package type devices package 10-bit adc port a port b port c port d total i/o z8f1232, z8f0830, z8f0430, Z8F0230, z8f0130 20-pin yes [7:0] [3:0] [3:0] [0] 17 z8f1233, z8f0831 z8f0431, z8f0231 z8f0131 20-pin no [7:0] [3:0] [3:0] [0] 17 z8f1232, z8f0830, z8f0430, Z8F0230, z8f0130 28-pin yes [7:0] [5:0] [7:0] [0] 23 z8f1233, z8f0831 z8f0431, z8f0231 z8f0131 28-pin no [7:0] [7:0] [7:0] [0] 25 note: 20-pin and 28-pin and 10-bit adc enabled or disabled can be selected via the option bits.
ps025113-1212 architecture z8 encore! ? f0830 series product specification 34 architecture figure 8 displays a simplified block diagram of a gpio port pin. in this figure, the ability to accommodate alternate functions and variab le port current drive strength is not dis- played. gpio alternate functions many of the gpio port pins can be used for general purpose input/output and access to on- chip peripheral functions such as the timers and serial communicatio n devices. the port a?d alternate function subregisters configure these pins for either gpio or alternate function operation. when a pin is configured fo r alternate function, co ntrol of the port pin direction (input/output) is passed from the port a?d data direction registers to the alter- nate function assign ed to this pin. table 16 on page 36 lists the alternate functions possible with each port pin. the alternate function associ ated at a pin is defined through alternate function subregisters afs1 and afs2. the crystal oscillator fu nctionality is not controlled by th e gpio block. when the crystal oscillator is enabled in the os cillator control block, the gpio functionality of pa0 and pa1 is overridden. in that case, pins pa0 and pa1 functions as in put and output for the crystal oscillator. figure 8. gpio port pin block diagram dq dq dq gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt trigger
ps025113-1212 direct led drive z8 encore! ? f0830 series product specification 35 pa0 and pa6 contain two different timer functions, a timer input and a complementary timer output. both of these fu nctions require the same gpio configuration, the selection between the two is based on the ti mer mode. for more details, see the timers chapter on page 68. direct led drive the port c pins provide a sinked current output, capable of driving an led without requiring an external resistor. the output sinks current at programmable levels, 3 ma, 7 ma, 13 ma and 20 ma. this mode is enabled through the led control registers. for proper function, the led anode must be connected to v dd and the cathode to the gpio pin. using all port c pins in led drive mode w ith maximum current may result in excessive total current. see the electrical characteristics chapter on page 184 for the maximum total current for the applicable package. shared reset pin on the 20- and 28-pin devices, the port d0 pin shares function with a bidirectional reset pin. unlike all other i/o pins, this pin does not default to gpio function on power-up. this pin acts as a bidirectional input/output open-drain reset with an internal pull-up until the user software reconfigures it as a gpio pd0. when in gpio mode, the port d0 pin functions as output only, and must be configured as an output. pd0 supports the high drive feature, but not the stop -mode recovery feature. crystal oscillator override for systems using a crystal oscillator, the pins pa0 and pa1 are connected to the crystal. when the crystal oscillator is enabled, the gpio settings ar e overridden and pa0 and pa1 are disabled. see the oscillator control register definitions section on page 154. 5 v tolerance in the 20- and 28-pin versions of this device, any pin, which shares functionality with an adc, crystal or comparator port is not 5 v-tolerant, including pa[1:0], pb[5:0] and pc[2:0]. all other signal pins are 5 v-tolerant and can safely handle inputs higher than v dd even with the pull-ups enabled, but with excess power consump tion on pull-up resis- tor.
ps025113-1212 external clock setup z8 encore! ? f0830 series product specification 36 external clock setup for systems using an external ttl drive, pb 3 is the clock source for 20- and 28-pin devices. in this case, configure pb3 for alte rnate function clkin. write to the oscillator control register (see the oscillator control register definitions section on page 154) to select the pb3 as the system clock. table 16. port alternate function mapping port pin mnemonic alternate function description alternate function set register afs1 port a 1 pa0 t0in/t0out timer 0 input/timer 0 output complement n/a reserved pa1 t0out timer 0 output reserved pa2 reserved reserved reserved pa3 reserved reserved reserved pa4 reserved reserved reserved pa5 reserved reserved reserved pa6 t1in/t1out timer 1 input/timer 1 output complement reserved pa7 t1out timer 1 output reserved notes: 1. because there is only a single alternate function for each port a and port d (pd0) pin, the alternate function set registers are not implemented for port a and port d (pd0). enabling alternate function selections (as described in the port a?d alternate function subregisters section on page 42) automatically enables the asso- ciated alternate function. 2. because there are at most two choices of alternate functi ons for any port b pin, the afs2 alternate function set register is implemented but is not used to select the function. additionally, alternate function selection (as described in the port a?d alternate function subregisters section on page 42) must also be enabled. 3. because there are at most two choices of alternate functi ons for any port c pin, the afs2 alternate function set register is implemented but is not used to select the function. additionally, alternate function selection (as described in the port a?d alternate function subregisters section on page 42) must also be enabled.
ps025113-1212 external clock setup z8 encore! ? f0830 series product specification 37 port b 2 pb0 reserved af s1[0]: 0 ana0 adc analog input afs1[0]: 1 pb1 reserved af s1[1]: 0 ana1 adc analog input afs1[1]: 1 pb2 reserved af s1[2]: 0 ana2 adc analog input afs1[2]: 1 pb3 clkin external inpu t clock afs1[3]: 0 ana3 adc analog input afs1[3]: 1 pb4 reserved af s1[4]: 0 ana7 adc analog input afs1[4]: 1 pb5 reserved af s1[5]: 0 v ref adc reference voltage afs1[5]: 1 pb6 reserved af s1[6]: 0 reserved afs1[6]: 1 pb7 reserved af s1[7]: 0 reserved afs1[7]: 1 table 16. port alternate function mapping (continued) port pin mnemonic alternate function description alternate function set register afs1 notes: 1. because there is only a single alternate function for each port a and port d (pd0) pin, the alternate function set registers are not implemented for port a and port d (pd0). enabling alternate function selections (as described in the port a?d alternate function subregisters section on page 42) automatically enables the asso- ciated alternate function. 2. because there are at most two choices of alternate functi ons for any port b pin, the afs2 alternate function set register is implemented but is not used to select the function. additionally, alternate function selection (as described in the port a?d alternate function subregisters section on page 42) must also be enabled. 3. because there are at most two choices of alternate functi ons for any port c pin, the afs2 alternate function set register is implemented but is not used to select the function. additionally, alternate function selection (as described in the port a?d alternate function subregisters section on page 42) must also be enabled.
ps025113-1212 external clock setup z8 encore! ? f0830 series product specification 38 port c 3 pc0 reserved afs1[0]: 0 ana4/cinp adc or comparator input afs1[0]: 1 pc1 reserved afs1[1]: 0 ana5/cinn adc or comparator input afs1[1]: 1 pc2 reserved afs1[2]: 0 ana6 adc analog input afs1[2]: 1 pc3 cout comparator output afs1[3]: 0 reserved afs1[3]: 1 pc4 reserved afs1[4]: 0 afs1[4]: 1 pc5 reserved afs1[5]: 0 afs1[5]: 1 pc6 reserved afs1[6]: 0 afs1[6]: 1 pc7 reserved afs1[7]: 0 afs1[7]: 1 port d 1 pd0 reset default to be reset function n/a table 16. port alternate function mapping (continued) port pin mnemonic alternate function description alternate function set register afs1 notes: 1. because there is only a single alternate function for each port a and port d (pd0) pin, the alternate function set registers are not implemented for port a and port d (pd0). enabling alternate function selections (as described in the port a?d alternate function subregisters section on page 42) automatically enables the asso- ciated alternate function. 2. because there are at most two choices of alternate functi ons for any port b pin, the afs2 alternate function set register is implemented but is not used to select the function. additionally, alternate function selection (as described in the port a?d alternate function subregisters section on page 42) must also be enabled. 3. because there are at most two choices of alternate functi ons for any port c pin, the afs2 alternate function set register is implemented but is not used to select the function. additionally, alternate function selection (as described in the port a?d alternate function subregisters section on page 42) must also be enabled.
ps025113-1212 gpio interrupts z8 encore! ? f0830 series product specification 39 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins can be con- figured to generate an interrupt request on either the rising ed ge or falling edge of the input pin signal. other port pin interrupt sources, ge nerate an interrupt when any edge occurs (both rising and falling). see the interrupt controller chapter on page 53 for more informa- tion about interrupts using the gpio pins. gpio control register definitions four registers for each port provide access to gpio control, input data and output data; table 17 lists these port registers. use the port a?d address and control registers together to provide access to subregiste rs for port configuration and control. table 17. gpio port registers and subregisters port register mnemonic port register name p x addr port a?d address register (selects subregisters) p x ctl port a?d control register (provides access to subregisters) p x in port a?d input data register p x out port a?d output data register port subregister mnemonic port register name p x dd data direction p x af alternate function p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recovery source enable p x pue pull-up enable pxafs1 alternate function set 1 pxafs2 alternate function set 2
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 40 port a?d address registers the port a?d address registers select the gp io port functionality accessible through the port a?d control registers. the port a?d address and control registers combine to pro- vide access to all gpio port controls; see tables 18 and 19. table 18. port a?d gpio address registers (p x addr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd0h, fd4h, fd8h, fdch bit description [7:0] ? paddr port address the port address selects one of the subregisters accessible through the port control register. table 19. port contro l subregis ter access paddr[7:0] port control subregister accessi ble using the port a?d control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction 02h alternate function 03h output control (open-drain) 04h high drive enable 05h stop mode recove ry source enable 06h pull-up enable 07h alternate function set 1 08h alternate function set 2 09h?ffh no function
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 41 port a?d control registers the port a?d control registers, shown in ta ble 20, set the gpio port operation. the value in the corresponding po rt a?d address register determines which subregister is read from or written to by a port a?d control register transaction. port a?d data dire ction subregisters the port a?d data direction subregister, show n in table 21, is accessed through the port a?d control register by writing 01h to the port a?d address register. table 20. port a?d control registers (p x ctl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd1h, fd5h, fd9h, fddh bit description [7:0] ? pctl port control the port control register provides access to all subregisters that configure the gpio port operation. table 21. port a?d data di rection subregisters (pxdd) bit 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 01h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? ddx data direction these bits control the direction of the associated port pin. port alternate function operation overrides the data direction register setting. 0 = output. data in the port a?d output data register is driven onto the port pin. 1 = input. the port pin is sampled and the value written into the port a?d input data register. the output driver is tristated. note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 42 port a?d alternate fu nction subregisters the port a?d alternate function subregiste r is accessed through the port a?d control register by writing 02h to the port a?d address register. see table 22 on page 42. the port a?d alternate function su bregisters enable the altern ate function selection on pins. if disabled, the pins function as gpios. if enab led, select one of four alternate functions using alternate function se t subregisters 1 and 2, as described in the the port a?d alter- nate function set 1 subregisters section on page 47 and the port a?d alternate function set 2 subregisters section on page 48 . see the gpio alternate functions section on page 34 to determine the alternate fu nctions associated with each port pin. do not enable alternate functio ns for gpio port pins for which there is no associated al- ternate function. failure to follow this gu ideline can result in unpredictable operation. table 22. port a?d alternate function subregisters (pxaf) bit 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 00h (ports a?c); 01h (port d) r/w r/w address if 02h in port a?d address register, then accessible through the port a?d control register bit description [7:0] ? afx port alternate function enable 0 = the port pin is in normal mode and the ddx bit in the port a?d da ta direction subregis- ter determines the direction of the pin. 1 = the alternate function selected through altern ate function set subregisters is enabled. port pin operation is controlled by the alternate function. note: x indicates the specific gpio port pin number (7?0). caution:
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 43 port a?d output c ontrol subregisters the port a?d output control subregister, show n in table 23, is accessed through the port a?d control register by writing 03h to the port a?d address register. setting the bits in the port a?d output control subr egisters to 1 configures the specified port pins for open- drain operation. these subregisters affect the pi ns directly and, as a result, alternate func- tions are also affected. table 23. port a?d output control subregisters (pxoc) bit 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 03h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? pocx port output control these bits function independently of the alternate function bit and always disable the drains, if set to 1. 0 = the drains are enabled for any output m ode (unless overridden by the alternate func- tion). 1 = the drain of the associated pin is disabled (open-drain mode). note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 44 port a?d high drive enable subregisters the port a?d high drive enable subregister, shown in table 24, is accessed through the port a?d control register by writing 04h to the port a?d address register. setting the bits in the port a?d high driv e enable subregisters to 1 conf igures the specified port pins for high-output current drive operation. the port a?d high drive enable subregister affects the pins directly and, as a resu lt, alternate functions are also affected. table 24. port a?d high drive enable subregisters (pxhde) bit 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 04h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? phdex port high drive enable 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 45 port a?d stop mode recovery source enable subregisters the port a?d stop mode recovery source en able subregister, shown in table 25, is accessed through the port a?d control register by writing 05h to the port a?d address register. setting the bits in the port a?d stop mode recovery source enable subregisters to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enable d as a stop mode recovery source initiates a stop mode recovery event. table 25. port a?d stop mode recovery source enable subregisters (pxsmre) bit 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 05h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? psmrex port stop mode recovery source enable 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin dur- ing stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mode recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 46 port a?d pull-up enable subregisters the port a?d pull-up enable subregister is accessed throug h the port a?d control reg- ister by writing 06h to the port a?d address register. see table 26. setting the bits in the port a?d pull-up enable subreg isters enables a weak intern al resistive pull-up on the specified port pins. table 26. port a?d pull-up enable subregisters (pxpue) bit 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 06h in port a ? d address register, accessible through the port a ? d control register bit description [7:0] ? p x pue port pull-up enable 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 47 port a?d alternate func tion set 1 subregisters the port a?d alternate function set 1 subr egister, shown in table 27, is accessed through the port a?d cont rol register by writing 07h to the port a?d address register. the alternate function set 1 subregisters select the alternate function available at a port pin. alternate functions selected by setting or clearing bits in this register are defined in the gpio alternate functions section on page 34. alternate function selection on the port pins must also be enabled, as described in the port a?d alternate function subregisters section on page 42. table 27. port a?d alternate function set 1 subregisters (pxafs1) bit 7 6 5 4 3 2 1 0 field pafs17 pafs16 pafs15 pafs14 pafs13 pafs12 pafs11 pafs10 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 07h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? pafs1x port alternate function set 1 0 = port alternate function selected as defined in table 16 in gpio alternate functions sec- tion. 1 = port alternate function selected as defined in table 16 in gpio alternate functions sec- tion. note: x indicates the specific gpio port pin number (7?0). note:
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 48 port a?d alternate func tion set 2 subregisters the port a?d alternate function set 2 subr egister, shown in table 28, is accessed through the port a?d cont rol register by writing 08h to the port a?d address register. the alternate function set 2 subregisters select the alternate function available at a port pin. alternate functions selected by setting or clearing bits in this register are defined in table 16 in the gpio alternate functions section on page 34. alternate function selection on the port pins must also be enabled, as described in the port a?d alternate function subregisters section on page 42. table 28. port a?d alternate function set 2 subregisters (pxafs2) bit 7 6 5 4 3 2 1 0 field pafs27 pafs26 pafs25 pafs24 pafs23 pafs22 pafs21 pafs20 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 08h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? pafs2x port alternate function set 2 0 = the port alternate function is selected, as defined in table 16 in the gpio alternate func- tions section on page 34. 1 = the port alternate function is selected, as defined in table 16 in the gpio alternate func- tions section on page 34. note: x indicates the specific gpio port pin number (7?0). note:
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 49 port a?c input data registers reading from the port a?c input data registers, shown in table 29, return the sampled values from the corresponding po rt pins. the port a?c input data registers are read-only. the value returned for any unu sed ports is 0. unused ports include those not included in the 8- and 28-pin packages, as well as those not included in the adc -enabled 28-pin pack- ages. table 29. port a?c input data registers (pxin) bit 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr address fd2h, fd6h, fdah bit description [7:0] ? pxin port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 50 port a?d output data register the port a?d output data register, shown in table 30, controls the output data to the pins. table 30. port a?d output data register (p x out) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd3h, fd7h, fdbh, fdfh bit description [7:0] ? pxout port output data these bits contain the data to be driven to the po rt pins. the values are only driven if the corre- sponding pin is configured as an output and t he pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is not driven if the drain has been disabled by setting the corresponding port output control register bit to 1. note: x indicates the specific gpio port pin number (7?0).
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 51 led drive enable register the led drive enable register, shown in tabl e 31, activates the controlled current drive. the alternate function register has no control over the led function; therefore, setting the alternate function register to select th e led function is not required. leden bits [7:0] correspond to port c bits [7:0], respectively. led drive level high register the led drive level high register, shown in table 32, contains two control bits for each port c pin. these two bits select one of f our programmable current drive levels for each port c pin. each pin is individually programmable. table 31. led drive enable (leden) bit 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f82h bit description [7:0] ? leden led drive enable these bits determine which port c pins are connected to an internal current sink. 0 = tristate the port c pin. 1= connect controlled current sink to the port c pin. table 32. led drive level high register (ledlvlh) bit 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f83h bit description [7:0] ? ledlvlh led level high bits {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma. 01= 7 ma. 10= 13 ma. 11= 20 ma.
ps025113-1212 gpio control register definitions z8 encore! ? f0830 series product specification 52 led drive level low register the led drive level low register , shown in table 33, contains two control bits for each port c pin. these two bits select one of f our programmable current drive levels for each port c pin. each pin is individually programmable. table 33. led drive level low register (ledlvll) bit 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f84h bit description [7:0] ? ledlvll led level low bits {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma. 01 = 7 ma. 10 = 13 ma. 11 = 20 ma.
ps025113-1212 interrupt controller z8 encore! ? f0830 series product specification 53 interrupt controller the interrupt controlle r on the z8 encore! ? f0830 series products pr ioritize the interrupt requests from the on-chip peripherals and the gp io port pins. the features of the interrupt controller include: ? seventeen interrupt sources using sixteen unique interrupt vectors: ? twelve gpio port pin interrupt sources ? five on-chip peripheral interrupt sources (comparator output interrupt shares one interrupt vector with pa6) ? ? flexible gpio interrupts ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? ? three levels of individually programmable interrupt priority ? watchdog timer can be configur ed to generate an interrupt ? m interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information or control infor- mation between the cpu and the interrupting pe ripheral. when the service routine is com- pleted, the cpu returns to the operation from wh ich it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt controller has no effect on oper ation. for more information about interrupt servicing by the ez8 cpu, refer to the ez8 cpu user manual (um0128) , which is avail- able for download at www.zilog.com . interrupt vector listing table 34 lists the interrupts available in order of priority. the interrupt vector is stored with the most significant byte (msb) at the even program memory address and the least significant byte (lsb) at the odd program memory address. some port interrupts are not available on th e 20-pin and 28-pin packages. the adc inter- rupt is unavailable on devices not containing an adc. note:
ps025113-1212 interrupt vector listing z8 encore! ? f0830 series product specification 54 table 34. trap and interrupt vectors in order of priority priority program memory ? vector address interrupt or trap source highest 0002h reset (not an interrupt) 0004h watchdog timer (see watchdog timer chapter) 003ah primary oscillator fail trap (not an interrupt) 003ch watchdog oscillator fail trap (not an interrupt) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh reserved 0010h reserved 0012h reserved 0014h reserved 0016h adc 0018h port a7, selectable rising or falling input edge 001ah port a6, selectable rising or fa lling input edge or comparator output 001ch port a5, selectable rising or falling input edge 001eh port a4, selectable ri sing or falling input edge 0020h port a3, selectable rising or falling input edge 0022h port a2, selectable rising or falling input edge 0024h port a1, selectable rising or falling input edge 0026h port a0, selectable rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c3, both input edges 0032h port c2, both input edges 0034h port c1, both input edges 0036h port c0, both input edges lowest 0038h reserved
ps025113-1212 architecture z8 encore! ? f0830 series product specification 55 architecture figure 9 displays the interru pt controller block diagram. operation this section describes th e operational aspects of the following functions. master interrupt enable : see page 55 interrupt vectors and priority : see page 56 interrupt assertion : see page 56 software interrupt assertion : see page 57 master interrupt enable the master interrupt enable bit (irqe) in the interrupt control register globally enables and disables the interrupts. interrupts are globally enabled by any of the following actions: ? execution of an ei (ena ble interrupt) instruction ? execution of an iret (return from interrupt) instruction figure 9. interrupt controller block diagram vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps025113-1212 operation z8 encore! ? f0830 series product specification 56 ? writing 1 to the irqe bit in the interrupt control register ? interrupts are globally disabled by any of the following actions: ? execution of a di (disable interrupt) instruction ? ez8 cpu acknowledgement of an interrupt service request from th e interrupt control- ler ? writing a 0 to the irqe bit in the interrupt control register ? reset ? execution of a trap instruction ? illegal instruction trap ? primary oscillator fail trap ? watchdog oscillator fail trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority an d level 1 is the lowest priority. if all of the interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for exam- ple), the interrupt priority is assigned from highest to lowest as specified in table 34 on page 54. level 3 interrupts are always assigned higher priority than level 2 interrupts and level 2 interrupts are assigned higher priority than level 1 interrupts. within each interrupt priority level (level 1, level 2 or level 3), priority is assigned as specified in table 34, above. reset, watchdog timer interrupt (if enabled), primary oscillator fail trap, watch- dog oscillator fail trap and illegal instruction trap always have highest (level 3) priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). when the interrupt request is ac knowledged by the ez8 cpu, the correspond- ing bit in the interrupt request register is cl eared. writing 0 to the corresponding bit in the interrupt request register clears the interrupt request. zilog recommends not using a coding style that clears bits in the interrupt request reg- isters. all incoming interrupt s received between execution of the first ldx command and the final ldx comm and are lost. see example 1, which follows. example 1. a poor coding style that can re sult in lost interrupt requests: caution:
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 57 ldx r0, irq0 ? and r0, mask ? ldx irq0, r0 ? to avoid missing interrupts, use the coding styl e in example 2 to clear bits in the interrupt request 0 register: example 2. a good coding style that av oids lost interrupt requests: andx irq0, mask software interrupt assertion program code can generate interrupts directly. writing 1 to the correct bit in the interrupt request register triggers an interrupt (assuming that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. zilog recommends not using a coding style to generate software interrupts by setting bits in the interrupt request registers. all inco ming interrupts received between execution of the first ldx command and the final ldx co mmand are lost. see example 3, which fol- lows. example 3. a poor coding style that can re sult in lost interrupt requests: ldx r0, irq0 ? or r0, mask ? ldx irq0, r0 to avoid missing interrupts, use the coding styl e in example 4 to set bits in the interrupt request registers: example 4. a good coding style that av oids lost interrupt requests: orx irq0, mask interrupt control register definitions the interrupt control registers enable indivi dual interrupts, set interrupt priorities and indicate interrupt requests for all of the interrupts other than the watchdog timer interrupt, the primary oscillator fail trap and the watchdog osc illator fail trap interrupts. caution:
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 58 interrupt requ est 0 register the interrupt request 0 (irq0) register, shown in table 35 stores the interrupt requests for both vectored and polled interrupts. when a request is sent to the interrupt controller, the corresponding bit in the irq0 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the ez8 cpu. if interrupts are globally disabled (polled in terrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending. table 35. interrupt request 0 register (irq0) bit 7 6 5 4 3 2 1 0 field reserved t1i t0i reserved adci reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc0h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1i timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. [5] ? t0i timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. [4:1] reserved these registers are reserved and must be programmed to 0000. [0] ? adci adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. 1 = an interrupt request from the analog -to-digital converter is awaiting service.
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 59 interrupt requ est 1 register the interrupt request 1 (irq1) register, shown in table 36, stores interrupt requests for both vectored and polled interrupts. when a requ est is sent to the interrupt controller, the corresponding bit in the irq1 register becomes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. table 36. interrupt request 1 register (irq1) bit 7 6 5 4 3 2 1 0 field pa7i pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc3h bit description [7] ? pa7i port a7 0 = no interrupt request is pending for gpio port a. 1 = an interrupt request from gpio port a. [6] ? pa6ci port a6 or comparator interrupt request 0 = no interrupt request is pending for gpio port a or comparator. 1 = an interrupt request from gpio port a or comparator. [5] ? paxi port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x. 1 = an interrupt request from gpio port a pin x is awaiting service. note: x indicates the specific gpio port pin number (5?0).
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 60 interrupt requ est 2 register the interrupt request 2 (irq2) register, shown in table 37, stores interrupt requests for both vectored and polled interrupts. when a requ est is sent to the interrupt controller, the corresponding bit in the irq2 register becomes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. irq0 enable high and low bit registers table 38 lists the priority control values for irq0. the irq0 enable high and low bit registers, shown in tables 39 and 40, form a priority-encoded enabling service for inter- rupts in the interrupt request 0 register. prior ity is generated by se tting the bits in each register. table 37. interrupt request 2 register (irq2) bit 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc6h bit description [7:4] reserved these registers are reserved and must be programmed to 0000. [3] ? pc xi port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. note: x indicates the specific gpio port pin number (3?0). table 38. irq0 enable and priority encoding irq0enh[ x ] irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: x indicates the register bits in the range 7?0.
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 61 table 39. irq0 enable hi gh bit register (irq0enh) bit 7 6 5 4 3 2 1 0 field reserved t1enh t0enh reserved adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc1h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1enh timer 1 interrupt reque st enable high bit [5] ? t0enh timer 0 interrupt reque st enable high bit [4:1] reserved these registers are reserved and must be programmed to 0000. [0] ? adcenh adc interrupt request enable high bit table 40. irq0 enable low bit register (irq0enl) bit 7 6 5 4 3 2 1 0 field reserved t1enl t0enl reserved adcenl reset 00000000 r/w r r/w r/w r/w r/w r r r/w address fc2h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1enl timer 1 interrupt request enable low bit [5] ? t0enl timer 0 interrupt request enable low bit [4:1] reserved these registers are reserved and must be programmed to 0000. [0] ? adcenl adc interrupt request enable low bit
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 62 irq1 enable high and low bit registers table 41 describes the priority control for irq1. the irq1 enable high and low bit reg- isters, shown in tables 42 and 43, form a priority-encoded enabling service for interrupts in the interrupt request 1 register . priority is generated by set ting the bits in each register. table 41. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 11 level 3 high note: x indicates register bits in the address range 7?0. table 42. irq1 enable hi gh bit register (irq1enh) bit 7 6 5 4 3 2 1 0 field pa7enh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc4h bit description [7] ? pa7enh port a bit[7] interrupt request enable high bit [6] ? pa6cenh port a bit[7] or comparator interrupt request enable high bit [5:0] ? pa xenh port a bit[ x ] interrupt request enable high bit see the interrupt port select register for selecti on of either port a or port d as the interrupt source. note: x indicates register bits in the address range 5?0.
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 63 irq2 enable high and low bit registers table 44 describes the priority control for irq2. the irq2 enable high and low bit reg- isters, shown in tables 45 and 46, form a priority-encoded enabling service for interrupts in the interrupt request 2 register . priority is generated by set ting the bits in each register. table 43. irq1 enable low bit register (irq1enl) bit 7 6 5 4 3 2 1 0 field pa7enl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc5h bit description [7] ? pa7enl port a bit[7] interrupt request enable low bit [6] ? pa6cenl port a bit[7] or comparator interrupt request enable low bit [5:0] ? pa xenl port a bit[ x ] interrupt request enable low bit see the interrupt port select register for selecti on of either port a or port d as the interrupt source. note: x indicates register bits in the address range 5?0. table 44. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: x indicates register bits in the address range 7?0.
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 64 table 45. irq2 enable hi gh bit register (irq2enh) bit 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc7h bit description [7:4] reserved these registers are reserved and must be programmed to 0000. [3] ? c3enh port c3 interrupt requ est enable high bit [2] ? c2enh port c2 interrupt requ est enable high bit [1] ? c1enh port c1 interrupt requ est enable high bit [0] ? c0enh port c0 interrupt requ est enable high bit table 46. irq2 enable low bit register (irq2enl) bit 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc8h bit description [7:4] reserved these registers are reserved and must be programmed to 0000. [3] ? c3enl port c3 interrupt request enable low bit [2] ? c2enl port c2 interrupt request enable low bit [1] ? c1enl port c1 interrupt request enable low bit [0] ? c0enl port c0 interrupt request enable low bit
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 65 interrupt edge select register the interrupt edge select (irqes) register determines whether an in terrupt is generated for the rising edge or falling edge on the se lected gpio port a or port d input pin. see table 47. table 47. interrupt edge select register (irqes) bit 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fcdh bit description [7] ? ies x interrupt edge select x 0 = an interrupt request is generated on the falling edge of the pa x input or pdx. 1 = an interrupt request is generated on the rising edge of the pa x input or pdx. note: x indicates register bits in the address range 7?0.
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 66 shared interrupt select register the shared interrupt select (irqss) register determines the source of the padxs inter- rupts. see table 48. the shared interrupt sele ct register selects between port a and alter- nate sources for the individual interrupts. because these shared interrupts are edge-trigger ed, it is possible to generate an interrupt just by switching from one shared source to another. for this reason, an interrupt must be disabled before switching between sources. table 48. shared interrupt select register (irqss) bit 7 6 5 4 3 2 1 0 field reserved pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fceh bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? pa6cs pa6/comparator selection 0 = pa6 is used for the interrupt caused by pa6cs interrupt request. 1 = the comparator is used for the interrupt caused by pa6cs interrupt request. [5:0] reserved these registers are reserved and must be programmed to 000000.
ps025113-1212 interrupt control register definitions z8 encore! ? f0830 series product specification 67 interrupt control register the interrupt control (irqctl) register, shown in table 49, contains the master enable bit for all interrupts. table 49. interrupt control register (irqctl) bit 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr address fcfh bit description [7] ? irqe interrupt request enable this bit is set to 1 by executing an enable interr upts (ei) or interrupt return (iret) instruction or by a direct register write of 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an interrupt request, reset, or by a direct register write of a 0 to this bit. 0 = interrupts are disabled. 1 = interrupts are enabled. [6:0] reserved these registers are reserved and must be programmed to 0000000.
ps025113-1212 timers z8 encore! ? f0830 series product specification 68 timers the z8 encore! f0830 series products contain up to two 16-bit reloadable timers that can be used for timing, event counting or generation of pulse width modulated (pwm) signals. the timers feature include: ? 16-bit reload counter ? programmable prescaler with pre scale values ranging from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock gatin g or capture signal. external input pin sig- nal frequency is limited to a maximum of one-fourth the system clock frequency ? timer output pin ? timer interrupt architecture figure 10 displays the architecture of the timers.
ps025113-1212 operation z8 encore! ? f0830 series product specification 69 operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer resets back to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer co unts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer ge nerates an interrupt and the co unt value in the timer high and low byte registers is reset to 0001h . the timer is automatically disabled and stops counting. additionally, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer figure 10. timer block diagram 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer block system timer data block output control bus clock input gate input capture input timer interrupt timer output complement
ps025113-1212 operation z8 encore! ? f0830 series product specification 70 reload. for the timer output to make a state change at a one-shot time-out (rather than a single cycle pulse), first set the tpol bit in the timer control register to the start value before enabling one-shot mode. after starting the timer, set tpol to the opposite bit value. observe the following steps fo r configuring a timer for on e-shot mode and for initiat- ing the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode ? set the prescale value ? set the initial output level (hig h or low) if using the timer output alternate func- tion ? 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configur e the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in one-shot mode, the system clock always pr ovides the timer inpu t. the timer period is calculated with the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, th e timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and the counting resumes. additionally, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps for configuring a timer for continuous mode and for ini- tiating the count: 1. write to the timer control register to: one-shot mode time-out period (s) reload value start value ? ?? prescale ? system clock frequency (hz) ------------------------------------------------------------------------------------------------ - =
ps025113-1212 operation z8 encore! ? f0830 series product specification 71 ? disable the timer ? configure the timer for continuous mode ? set the prescale value ? if using the timer output a lternate function, set the initial output level (high or low) ? 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this action only affects the first p ass in continuous mode. after the first timer reload in continuous mode, countin g always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt (if appropriate) an d set the timer interrupt priority by writ- ing to the relevant interrupt registers. 5. configure the associated gpio port pin (i f using the timer output function) for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in continuous mode, the system clock alwa ys provides the timer input. the timer period is calculated w ith the follo wing equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equatio n to determine the first time-out period. counter mode in counter mode, the timer counts input tr ansitions from a gpio port pin. the timer input is taken from the gpio po rt pin: timer input alternate function. the tpol bit in the timer control register determin es whether the count occurs on the rising edge or the fall- ing edge of the timer input signal. in counter mode, the prescaler is disabled. the input frequency of the timer input sign al must not exceed one-fourth the system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. additionally, if the timer output alternate function continuous mode time-out period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ = caution:
ps025113-1212 operation z8 encore! ? f0830 series product specification 72 is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps for configuring a timer for counter mode and for initiat- ing the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for counter mode ? select either the rising edge or falling edge of the timer input signal for the count. this selection also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer output function is not required to be enabled. ? 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in coun- ter mode, counting always begins at the reset value 0001h . in counter mode, the timer high and low byte register s must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configur e the associated gpio port pin for the timer output alternate function. 7. write to the timer control re gister to enable the timer. ? in counter mode, the number of timer inpu t transitions is calcu lated with the follow- ing equation: comparator counter mode in comparator counter mode, the timer co unts the input transitions from the ana- log comparator output. the tpol bit in the timer control register determines whether the count occurs on the rising edge or the falling edge of the comparator output signal. in comparator counter mode, the prescaler is disabled. counter mode timer input transitio ns current count value start value ? =
ps025113-1212 operation z8 encore! ? f0830 series product specification 73 the frequency of the comparator output sign al must not exceed on e-fourth the system clock frequency. after reaching the reload valu e stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. additionally, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps for config uring a timer for comparator counter mode and for initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for co mparator counter mode. ? select either the rising edge or falling edge of the comparator output signal for the count. this also sets the initial logic leve l (high or low) for the timer output alter- nate function. however, the timer output function is no t required to be enabled. ? 2. write to the timer high and low byte regi sters to set the startin g count value. this action only affects the first pass in co mparator counter mode. after the first timer reload in comparator counter mode, counting always begins at the reset value 0001h . generally, in comparator counter mode, the timer high and low byte registers must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configur e the associated gpio port pin for the timer output alternate function. 6. write to the timer control re gister to enable the timer. ? in comparator counter mode, the number of comparator output transitions is cal- culated with the following equation: caution: comparator output transitions cu rrent count value start value ? =
ps025113-1212 operation z8 encore! ? f0830 series product specification 74 pwm single output mode in pwm single output mode, the timer outputs a pulse width modulated (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to 16-bit pwm match value stored in the timer pwm high and low byte regis- ters. when the timer count value matches th e pwm value, the timer output toggles. the timer continues counting until it re aches the reload value stored in the timer reload high and low byte registers. upon reaching the re load value, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after th e timer reaches the reload value and is reset to 0001h . observe the following steps for configur ing a timer for pwm single output mode and for initiating pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm mode ? set the prescale value ? set the initial logic level (high or low) and pwm high/low transition for the timer output alternate function ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). this value only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation:
ps025113-1212 operation z8 encore! ? f0830 series product specification 75 if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm time-out period. if tpol bit is set to 0, the ratio of the pwm output high time to the total period is repre- sented by: if tpol bit is set to 1, the ratio of the pwm output high time to the total period is repre- sented by: pwm dual output mode in pwm dual output mode, the timer outp uts a pwm output signal pair (basic pwm signal and its complement) through two gpio port pins. the timer input is the sys- tem clock. the timer first counts up to 16 -bit pwm match value stored in the timer pwm high and low byte registers. when the ti mer count value matches the pwm value, the timer output toggles. the timer continues counting until it reaches the reload value stored in the timer reload high and low byte registers. upon reac hing the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after th e timer reaches the reload value and is reset to 0001h . the timer also generates a second pwm output signal: the timer output complement. the timer output complement is the complement of the timer output pwm signal. a program- mable deadband delay can be configured to time delay (0 to 128 system clock cycles) pwm output transitions on these two pins fro m a low to a high (inactive to active) to ensure a time gap between the deassertion of one pwm output to th e assertion of its com- plement. pwm period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ = pwm output high time ratio (%) reload value pwm value ? reload value -------------------------------------------------------------------- - 100 ? = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 ? =
ps025113-1212 operation z8 encore! ? f0830 series product specification 76 observe the following steps for configuring a timer for pwm dual output mode and for initiating the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm dual ou tput mode; setting the mode also involves writing to tmodehi bit in the txctl1 register ? set the prescale value ? set the initial logic level (high or low) and pwm high/low transition for the timer output alternate function ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). this write only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the pwm control register to se t the pwm deadband delay value. the dead- band delay must be less than the duration of the positive phase of the pwm signal (as defined by the pwm high and low byte register s). it must also be less than the dura- tion of the negative phase of the pwm sign al (as defined by the difference between the pwm registers and the timer reload registers). 5. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 6. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. configure the associated gpio port pin for the timer output and timer output comple- ment alternate functions. the timer output complement function is shared with the timer input function for both timers. settin g the timer mode to dual pwm will auto- matically switch the fu nction from timer-in to timer-out complement. 8. write to the timer control register to enable the timer and initiate counting. ? the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation determines the first pwm time-out period. if tpol is set to 0, the ratio of the pwm output hi gh time to the total period is represented by: pwm period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ =
ps025113-1212 operation z8 encore! ? f0830 series product specification 77 if tpol is set to 1, the ratio of the pwm output hi gh time to the total period is represented by: capture mode in capture mode, the current timer count valu e is recorded when the appropriate exter- nal timer input transition occurs. the capture coun t value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event occurs, an interrupt is generated and the timer continues counting. the inpcap bit in the txctl1 register is se t to indicate the timer interrupt because of an input capture event. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching th e reload value, the timer generates an inter- rupt and continues counting. the inpcap bit in the txctl1 register clears, indicating that the timer interrupt has not occurre d because of an input capture event. observe the following steps for configuring a timer for capture mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . clearing these registers allows user software to determine if inte rrupts were generated either by a capture event or by a reload. if the pwm high and low byte registers still contain 0000h after the interrupt, the interrupt were generated by a reload. pwm output high time ratio (%) reload value pwm value ? reload value -------------------------------------------------------------------- - 100 ? = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 ? =
ps025113-1212 operation z8 encore! ? f0830 series product specification 78 5. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting the ticonfig field of the txctl1 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. ? in capture mode, the elapsed time between th e timer start and the capture event can be calculated using the following equation: capture restart mode in capture restart mode, the current tim er count value is recorded when the acceptable external timer input transition occurs. the capture count value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control regist er determines whether the captu re occurs on a rising edge or a falling edge of the timer input signal. wh en the capture event oc curs, an interrupt is generated and the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in the tx ctl1 register is set to indicate that the timer interrupt has been caused by an input capture event. if no capture event occurs, the timer counts up to 16-bit compare valu e stored in the timer reload high and low byte registers. upon reac hing the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in the txctl1 register is cleared to indicate that the timer interrupt has not been ca used by an input capture event. observe the following steps for configuring a timer for capture restart mode and for initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture r estart mode; setting the mode also involves writing to tmodehi bit in the txctl1 register ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps025113-1212 operation z8 encore! ? f0830 series product specification 79 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows user soft- ware to determine if interrupts are generate d by either a capture event or a reload. if the pwm high and low byte registers still contain 0000h after the interrupt, the interrupt were generated by a reload. 5. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events. the user ca n configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting the ticonfig field of the txctl1 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. ? in capture mode, the elapsed time between th e timer start and the capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and counting continues (the timer value is not reset to 0001h ). additionally, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon compare. if the timer reaches ffffh , the timer resets to 0000h and continues counting. observe the following steps for configuring a timer for compare mode and for initiat- ing the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode ? set the prescale value ? set the initial logic level (high or low) for the timer output alternate function ? 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps025113-1212 operation z8 encore! ? f0830 series product specification 80 4. enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configur e the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in compare mode, the system clock always provides the timer inpu t. the compare time can be calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine wh ether the timer input signal deassertion generated the interrupt, read the associated gpio input value and com- pare to the value stored in the tpol bit. the timer counts up to the 16-bit reload value stored in th e timer reload high and low byte registers. the timer inpu t is the system clock. upon re aching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the tim er input signal remains asserted). additionally, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reset. observe the following steps for configuring a timer for gated mode and for initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for gated mode ? set the prescale value ? 2. write to the timer high and low byte registers to set the starting count value. writing these registers only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. by default, the timer in terrupt is generated for both input deasser- compare mode time (s) compare value start value ? ?? prescale ? system clock frequency (hz) ----------------------------------------------------------------------------------------------------- - =
ps025113-1212 operation z8 encore! ? f0830 series product specification 81 tion and reload events. the user can configur e the timer interrupt to be generated only at the input deassertion event or the reload event by setting the ticonfig field of the txctl1 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control re gister to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, th e timer begins counting on the first external timer input transition. the acceptable transition (rising edge or falling edge) is set by the tpol bit in the timer control register. th e timer input is th e system clock. every subsequent acceptable transition (after th e first) of the timer input signal, captures the current count value. the capture value is written to the timer pwm high and low byte registers. when the capture event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to 0001h and the counting resumes. the inpcap bit in the txctl1 register is set to in dicate that the timer in terrupt is caused by an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in the txctl1 register is cleared to indi- cate that the timer interrupt has not be en caused by an input capture event. observe the following steps for configurin g a timer for capture/compare mode and for initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers.by default, the timer interrupt are generated for both input capture and reload events. the user can configure th e timer interrupt to be generated only at the input capture event or the reload even t by setting ticonfig field of the txctl1 register. 5. configure the associated gpio port pi n for the timer input alternate function.
ps025113-1212 operation z8 encore! ? f0830 series product specification 82 6. write to the timer control re gister to enable the timer. 7. counting begins on the first appropriate tr ansition of the timer in put signal. no inter- rupt is generated by the first edge. ? in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when the timer is enabled and the timer high byte reg- ister is read, the contents of the timer low by te register are placed in a holding register. a subsequent read from the timer low byte register returns the value in the holding register. this operation allows accurate reads of the full 16-bit time r count value when enabled. when the timers are not enabled, a read from th e timer low byte register returns the actual value in the counter. timer pin signal operation timer output is a gpio port pin alternate func tion. the timer output is toggled every time the counter is reloaded. the timer input can be used as a selectable counting source. it shares the same pin as the complementary timer output. when selected by the gpio alternate function registers, this pin functions as a timer in put in all modes except for the dual pwm output mode. for this mode, no time r input is available. capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 83 timer control register definitions this section defines the features of the following timer control registers. timer 0?1 high and low byte registers : see page 83 timer reload high and low byte registers : see page 85 timer 0?1 pwm high and low byte registers : see page 86 timer 0?1 control registers : see page 87 timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and txl) registers, shown in tables 50 and 51, contain the current 16-bit timer count value. when the timer is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from txl always returns this temporary register conten t when the timer is enabled; however, when the timer is disabled, a read from the tx l reads the txl register content directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regi sters available for write operations; there- fore, simultaneous 16-bit writes are not possible. if either the timer high or low byte registers are written during counting, the 8-bit written value is placed in the counter (high or low byte) at the next clock edge. the counter continues counting from the new value. table 50. timer 0?1 high byte register (txh) bit 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f00h, f08h table 51. timer 0?1 low byte register (txl) bit 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f01h, f09h
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 84 bit description [7:0] ? th, tl timer high and low bytes these 2 bytes, {th[7:0], tl[7:0]}, contain the current 16-bit timer count value.
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 85 timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers, shown in tables 52 and 53, store a 16-bit reload value, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stored in a temporary holding register. when a write to the timer reload low byte register occu rs, the temporary holding register value is written to the timer high byte register. this operation allows si multaneous updates of the 16-bit timer reload value. in compare mode, the timer reload high and low byte registers store the 16-bit compare value. table 52. timer 0?1 reload high byte register (txrh) bit 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f02h, f0ah table 53. timer 0?1 reload low byte register (txrl) bit 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f03h, f0bh bit description [7:0] ? trh, trl timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[7:0]}. this value sets the max- imum count value, which in itiates a timer reload to 0001h . in compare mode, these two bytes form the 16-bit compare value.
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 86 timer 0?1 pwm high and low byte registers the timer 0?1 pwm high and low byte (txpwmh and txpwml) registers, shown in tables 54 and 55, control pwm operations. the se registers also store the capture values for the capture and capture/compare modes. table 54. timer 0?1 pwm high byte register (txpwmh) bit 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f04h, f0ch table 55. timer 0?1 pwm low byte register (txpwml) bit 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f05h, f0dh bit description [7:0] ? pwmh, pwml pulse width modulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16 -bit value that is compared to the current 16-bit timer count. when a match occurs, t he pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl1). the txpwmh and txpwml registers also store the 16-bit captured timer value when operat- ing in capture or c apture/compare modes.
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 87 timer 0?1 control registers the timer control registers are 8-bit read/write registers that control the operation of their associated counter/timers. time 0?1 control register 0 the timer control 0 (txctl0) and timer control 1 (txctl1) registers determine the timer operating mode. these registers also include a programmable pwm deadband delay, two bits to configure the timer interrupt defin ition, and a status bit to identify if the most recent timer interrupt is caused by an input capture event. table 56. timer 0?1 control register 0 (txctl0) bit 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f06h, f0eh bit description [7] ? tmodehi timer mode high bit this bit along with the tmode field in the tx ctl1 register determines the operating mode of the timer. this is the most significant bi t of the timer mode selection value. see the txctl1 register description on the next page for additional details. [6:5] ? ticonfig timer interrupt configuration this field configures ti mer interrupt definition. 0x = timer interrupt occurs on all of the defined reload, compare and input events. 10 = timer interrupt occurs only on defined input capture/deassertion events. 11 = timer interrupt occurs only on defined reload/compare events. [4] reserved this bit is reserved and must be programmed to 0. [3:1] ? pwmd pwm delay value this field is a programmable delay to cont rol the number of system clock cycles delay before the timer output and the timer output complement are forced to their active state. 000 = no delay. 001 = 2 cycles delay. 010 = 4 cycles delay. 011 = 8 cycles delay. 100 = 16 cycles delay. 101 = 32 cycles delay. 110 = 64 cycles delay. 111 = 128 cycles delay.
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 88 timer 0?1 control register 1 the timer 0?1 control (txctl1) registers en able/disable the timers, set the prescaler value, and determine the timer operating mode. [0] ? inpcap input capture event this bit indicates whether the most recent time r interrupt is caused by a timer input capture event. 0 = previous timer interrupt is not caused by timer input capture event. 1 = previous timer interrupt is caused by timer input capture event. table 57. timer 0?1 control register 1 (txctl1) bit 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f07h, f0fh bit description [7] ? ten timer enable 0 = timer is disabled. 1 = timer enabled to count. bit description (continued)
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 89 [6] ? tpol timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented on timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled and reloaded, the timer output signal is complemented. counter mode if the timer is disabled, the timer output signal is set to the value of this bit. if the timer is enabled the timer output signal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling ed ge of the timer input signal. pwm single output mode 0 = timer output is forced low (0), when the ti mer is disabled. the timer output is forced high (1) when the timer is enabled and the pwm count matches and the timer output is forced low (0) when the timer is enabled and reloaded. 1 = timer output is forced high (1), when the timer is disabled. the timer output is forced low(0), when the timer is enabled and the pwm count matches and forced high (1) when the timer is enabled and reloaded. capture mode 0 = count is captured on the risi ng edge of the timer input signal. 1 = count is captured on the fa lling edge of the ti mer input signal. compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled and reloaded, the timer output signal is complemented. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the timer input signal is low (0) and interrupts are generated on the ris- ing edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent rising ed ges of the timer input signal. 1 = counting is started on the first falling edge of the timer input signal. the current count is captured on s ubsequent falling edges of the timer input signal. bit description (continued)
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 90 [6] ? tpol (cont?d) pwm dual output mode 0 = timer output is forced low (0) and timer outp ut complement is forced high (1), when the timer is disabled. when enabled and the pwm count matches, the timer output is forced high (1) and forced low (0) when enabled and reloaded. when enabled and the pwm count matches, the timer output complement is forced low (0) and forced high (1) when enabled and reloaded. 1 = timer output is forced high (1) and timer output complement is forced low (0) when the timer is disabled. when enabled and the pwm count matches, the timer output is forced low (0) and forced high (1) when enabled and reloaded.when enabled and the pwm count matches, the timer output complement is forced high (1) and forced low (0) when enabled and reloaded. the pwmd field in the txctl0 register determines an optional added delay on the assertion (low to high) tran sition of both timer ou tput and timer output complement for deadband generation. capture restart mode 0 = count is captured on the risi ng edge of the timer input signal. 1 = count is captured on the fa lling edge of the ti mer input signal. comparator counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented on timer reload. ? caution: when the timer output alternate function txout on a gpio port pin is enabled, txout will change to whatever stat e the tpol bit is in. the time r does not need to be enabled for that to happen. additionally, the port data direction sub regist er is not needed to be set to output on txout. changing the tpol bit when the timer is enabled and running does not immediately change the polarity txout. [5:3] ? pres prescale value the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this reset ensures proper clock division each time the timer is restarted. 000 = divide by 1. 001 = divide by 2. 010 = divide by 4. 011 = divide by 8. 100 = divide by 16. 101 = divide by 32. 110 = divide by 64. 111 = divide by 128. bit description (continued)
ps025113-1212 timer control register definitions z8 encore! ? f0830 series product specification 91 [2:0] ? tmode timer mode this field along with the tmodehi bit in txctl0 register determines the operating mode of the timer. tmodehi is the most significan t bit of the timer mode selection value. 0000 = one-shot mode. 0001 = continuous mode. 0010 = counter mode. 0011 = pwm single output mode. 0100 = capture mode. 0101 = compare mode. 0110 = gated mode. 0111 = capture/compare mode. 1000 = pwm dual output mode. 1001 = capture restart mode. 1010 = comparator counter mode. bit description (continued)
ps025113-1212 watchdog timer z8 encore! ? f0830 series product specification 92 watchdog timer the watchdog timer (wdt) protects from corrupt ed or unreliable software, power faults and other system-level proble ms which can place the z8 encore! f0830 series devices into unsuitable operating states. the fe atures of the watchdog timer include: ? on-chip rc oscillator ? a selectable time-out response: reset or interrupt ? 24-bit programmable time-out value operation the watchdog timer is a retr iggerable one-shot timer that resets or interrupts the z8 encore! f0830 series devices when the wdt reaches its terminal count. the wdt uses a dedicated on-chip rc oscillator as its clock so urce. the wdt operates only in two modes: on and off. once enabled, it always counts an d must be refreshed to prevent a time-out. perform an enable by executing the wdt in struction or by setting the wdt_ao flash option bit. the wdt_ao bit forces the wdt to operate immediately on reset, even if a wdt instruction has not been executed. the watchdog timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is calculated using the following equation: where the wdt reload value is the 24-bit decimal value provided by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and the typical watchdog timer rc oscillator frequency is 10 khz. the watchdog timer cannot be refreshed after it reaches 000002h . the wdt reload value must not be set to values below 000004h . table 58 provides information about approximate time-out delays for th e minimum and maximum wdt reload values. table 58. watchdog timer approximate time-out delays wdt reload value (hex) wdt reload value (decimal) approximate time-out delay (with 10 khz typical wdt oscillator frequency) typical description 000004 4 400 s minimum time-out delay 000400 1024 102 ms default time-out delay ffffff 16,777,215 28 minutes maximum time-out delay wdt time-out period (ms) wdt reload value 10 ----------------------------------------------- - =
ps025113-1212 operation z8 encore! ? f0830 series product specification 93 watchdog timer refresh upon first enable, the watchdog timer is loaded with the value in the wa tchdog timer reload registers. the watchdog timer counts down to 000000h unless a wdt instruc- tion is executed by the ez8 cpu. execution of the wdt instruction causes the downcoun- ter to be reloaded with th e wdt reload value stored in the watchdog timer reload registers. counting resumes fo llowing the reload operation. when the z8 encore! f0830 series devices ar e operating in debug mode (using the on- chip debugger), the watchdog timer must be continuously refreshed to prevent any wdt time-outs. watchdog timer time-out response the watchdog timer times ou t when the counter reaches 000000h . a time-out of the watchdog timer generates either an interru pt or a system reset. the wdt_res flash option bit determines the time-out res ponse of the watchdog timer. see the flash option bits chapter on page 124 for information about programming the wdt_res flash option bit. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occu rs, the watchdog timer issues an interrupt request to the interrupt contro ller and sets the wdt status bit in the reset status register. if interrupts are enabled, the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and executing code from the vector address. after time-out and interrupt generation, the watchdog timer counter resets to its maxi- mum value of fffffh and continues counting. the watchdog timer counter will not automatically return to its reload value. the reset status register (see table 12 on page 29 ) must be read before clearing the wdt interrupt. this read clea rs the wdt time-out flag and prevents further wdt inter- rupts occurring immediately. wdt interrupt in stop mode if configured to generate an interrupt when a time-out occu rs and the z8 encore! f0830 series devices are in stop mode, the watc hdog timer automatically initiates a stop mode recovery and generates an interrupt request. both the wdt status bit and the stop bit in the watchdog timer control register are set to 1 following a wdt time-out in stop mode. see the reset and stop mode recovery chapter on page 21 for more infor- mation about stop mode recovery operations. if interrupts are enabled, following completi on of the stop mode recovery, the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and exe- cutes the code from the vector address.
ps025113-1212 operation z8 encore! ? f0830 series product specification 94 wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watc hdog timer forces the device into the system reset state. the wd t status bit in the watchdog timer control register is set to 1. see the reset and stop mode recovery chapter on page 21 for more information about system reset operations. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the device is in stop mode, the watchdog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the watchdog timer control regi ster are set to 1 following wdt time-out in stop mode. see the reset and stop mode recovery chapter on page 21 for more infor- mation about stop mode recovery operations. watchdog timer relo ad unlock sequence writing the unlock sequence to the watchd og timer (wdtctl) control register address, unlocks the three watchdog timer reload byte registers (wdtu, wdth and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. the following sequence is requir ed to unlock the watchdog timer reload byte registers (wdtu, wdth and wdtl) for write access: 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu). 4. write the watchdog timer reload high byte register (wdth). 5. write the watchdog timer relo ad low byte register (wdtl). ? all three watchdog timer reload registers mu st be written in the order listed above. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. the value in the watchdog timer re load registers is loaded into the counter when the watchdog timer is first enabled and every time a wdt instruction is executed.
ps025113-1212 watchdog timer control register definitions z8 encore! ? f0830 series product specification 95 watchdog timer control register definitions this section defines the features of the fo llowing watchdog timer control registers. watchdog timer control register (wdtctl) : see page 95 watchdog timer reload lo w byte register (wdtl) : see page 97 watchdog timer reload upper byte register (wdtu) : see page 96 watchdog timer reload high byte register (wdth) : see page 96 watchdog timer control register the watchdog timer control (wdtctl) register is a write-only control register. writ- ing the unlock sequence: 55h , aah to the wdtctl register address unlocks the three watchdog timer reload byte registers (wdt u, wdth and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address have no effect on the bits in the wdtctl register . the locking mechanism prevents spurious writes to the reload registers. this register address is shared with the read-only reset status register. table 59. watchdog timer control register (wdtctl) bit 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww address ff0h bit description [7:0] ? wdtunlk watchdog timer unlock the user software must write the correct unlocki ng sequence to this register before it is allowed to modify the contents of the watchdog timer reload registers.
ps025113-1212 watchdog timer control register definitions z8 encore! ? f0830 series product specification 96 watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, high and low byte (wdtu, wdth, wdtl) regis- ters, shown in tables 60 through 62, form the 24-bit reload value that is loaded into the watchdog timer when a wdt instruction executes. this 24-bit value ranges across bits [23:0] to encompass the three bytes {wdt u[7:0], wdth[7:0], wdtl[7:0]}. writing to these registers sets the appropriate reload value; reading from these registers returns the current watchdog timer count value. the 24-bit wdt reload value must not be set to a value less than 000004h . table 60. watchdog timer reload upper byte register (wdtu) bit 7 6 5 4 3 2 1 0 field wdtu reset 00000000 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff1h note: *a read returns the current wdt count valu e; a write sets the appropriate reload value. bit description [7:0] ? wdtu wdt reload upper byte most significant byte (msb), bits[23:16], of the 24-bit wdt reload value. table 61. watchdog timer reload high byte register (wdth) bit 7 6 5 4 3 2 1 0 field wdth reset 00000100 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff2h note: *a read returns the current wdt count valu e; a write sets the appropriate reload value. bit description [7:0] ? wdth wdt reload high byte middle byte, bits[15:8] of the 24-bit wdt reload value. caution:
ps025113-1212 watchdog timer control register definitions z8 encore! ? f0830 series product specification 97 table 62. watchdog timer reload low byte register (wdtl) bit 7 6 5 4 3 2 1 0 field wdtl reset 0000000 0 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff3h note: *a read returns the current wdt count valu e; a write sets the appropriate reload value. bit description [7:0] ? wdtl wdt reload low least significant byte (lsb), bits[7:0] of the 24-bit wdt reload value.
ps025113-1212 analog-to-digital converter z8 encore! ? f0830 series product specification 98 analog-to-digital converter the z8 encore! mcu includes an eight-chan nel successive approximation register (sar) analog-to-digital converter (adc). the adc converts an analog input signal to a 10-bit binary number. the features of the sar adc include: ? eight analog input sources multiple xed with general purpose i/o ports ? fast conversion time, less than 11.9 s ? programmable timing controls ? interrupt on conversion complete ? internal voltage re ference generator ? ability to select external reference voltage ? when configuring an adc using external v ref , pb5 is used as v ref in the 28-pin package architecture the adc architecture, displayed in figure 11, consists of an 8-input multiplexer, sample- and-hold amplifier and 10-bit sar adc. the adc digitizes the signal on a selected channel and stores the digitized data in the adc data registers. in an environment with high electrical noise, an extern al rc filter must be added at the input pins to reduce high- frequency noise. t conv = t s/h + t con t conv = t s + t h + 13 * sclk * 16 where: sclk = system clock t conv = total conversion time t s = sample time (sclk * adcst) t con = conversion time (13 * sclk * 16) t h = hold time (sclk * adcsst) div = 16 (fixed to divide by 16 for f0830 series products) ? example: for an f0830 series mcu running @ 20 mhz: t conv = 1s + 0.5s + 13 * sclk * div t conv = 1 s + 0.5 s + 13 * (1/20 mhz) * 16 = 11.9 s
ps025113-1212 operation z8 encore! ? f0830 series product specification 99 operation the adc converts the analog input, ana x , to a 10-bit digital representation. the equa- tion for calculating the digital value is represented by: assuming zero gain and offset errors, any voltage outside the adc input limits of av ss and v ref returns all 0s or 1s, respectively. a ne w conversion can be initiated by a soft- ware to the adc control register?s start bit. initiating a new conversion, stop s any conversion currently in progress and begins a new conversion. to avoid disrupting a conversion already in progress, the start bit can be read to determine adc operation status (busy or available). figure 11. analog-to-digital converter block diagram analog-to-digital converter ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 analog input multiplexer anain[2:0] internal voltage reference generator analog input reference input sample-and-hold amplifier data output 10 vr2 v ref rbuf refen sample/hold start adclk adcen busy sel 28 package adcoutput 1024 ana x v ref ? ?? ? =
ps025113-1212 operation z8 encore! ? f0830 series product specification 100 adc timing each adc measurement consists of three phases: 1. input sampling (programmable, minimum of 1.0 s) 2. sample-and-hold amplifier settling (programmable, minimum of 0.5 s) 3. conversion is 13 adclk cycles ? figures 12 and 13 display the timing of an adc conversion. figure 12. adc timing diagram figure 13. adc convert timing start sample/hold 1.0s min sample period programable settling period busy 13 clocks convert period conversion period busy 13 clocks convert period adc clock 12345678910111213141516 17 convertbit5 convertbit4 convertbit3 convertbit2 convertbit1 convertbit0 store in register sync convertbitmsb convertbit8 convertbit7 convertbit6 sync
ps025113-1212 adc control register definitions z8 encore! ? f0830 series product specification 101 adc interrupt the adc can generate an inte rrupt request when a conversion has been completed. an interrupt request that is pending when the ad c is disabled is not cleared automatically. reference buffer the reference buffer, rbuf, supplies the refe rence voltage for the adc. when enabled, the internal voltage reference generator su pplies the adc. when rbuf is disabled, the adc must have the reference voltage supplied externally through the v ref pin in 28-pin package. rbuf is controlled by the refen bit in the adc control register. internal voltage reference generator the internal voltage reference generator provides the voltage vr2, for the rbuf. vr2 is 2 v. calibration and compensation a user can perform calibration and store the va lues into flash or the user code can perform a manual offset calibration. there is no provision for manual gain calibration. adc control register definitions the adc control registers are defined in this section.
ps025113-1212 adc control register definitions z8 encore! ? f0830 series product specification 102 adc control register 0 the adc control 0 register, shown in table 63 , initiates an a/d conversion and provides adc status information. table 63. adc control register 0 (adcctl0) bit 7 6 5 4 3 2 1 0 field start reserved refen adce n reserved anain[2:0] reset 00000000 r/w r/w1 r/w r/w r/w r/w r/w r/w r/w address f70h bit description [7] ? start adc start/busy 0 = writing to 0 has no effect; reading a 0 indica tes that the adc is available to begin a conver- sion. 1 = writing to 1 starts a conversion; reading a 1 indicates that a conversion is currently in prog- ress. [6] reserved this bit is reserved and must be programmed to 0. [5] ? refen reference enable 0 = internal reference voltage is disabled allowing an external reference voltage to be used by the adc. 1 = internal reference voltage for the adc is enabled. the internal reference voltage can be measured on the v ref pin. [4] ? adcen adc enable 0 = adc is disabled for low power operation. 1 = adc is enabled for normal use. [3] reserved this bit is reserved and must be programmed to 0. [2:0] ? anain analog input select 000 = ana0 input is selected for analog to digital conversion. 001 = ana1 input is selected for analog to digital conversion. 010 = ana2 input is selected for analog to digital conversion. 011 = ana3 input is selected for analog to digital conversion. 100 = ana4 input is selected for analog to digital conversion. 101 = ana5 input is selected for analog to digital conversion. 110 = ana6 input is selected for analog to digital conversion. 111 = ana7 input is selected for analog to digital conversion.
ps025113-1212 adc control register definitions z8 encore! ? f0830 series product specification 103 adc data high byte register the adc data high byte register, listed in ta ble 64, contains the upper eight bits of the adc output. access to the adc data high byte register is read-only. reading the adc data high byte register latches da ta in the adc low bits register. adc data low bits register the adc data low bits register, shown in ta ble 65, contains the lower bits of the adc output. access to the adc data low bits regi ster is read-only. reading the adc data high byte register latches lower bits of the adc in the adc data low bits register. table 64. adc data high byte register (adcd_h) bit 7 6 5 4 3 2 1 0 field adcdh reset x r/w r address f72h bit description [7:0] ? adcdh adc high byte 00h?ffh = the last conversion output is held in the data registers until the next adc conver- sion is completed. table 65. adc data low bits register (adcd_l) bit 7 6 5 4 3 2 1 0 field adcdl reserved reset xx r/w rr address f73h bit description [7:6] ? adcdl adc low bits 00?11b = these bits are the two least-significant bits of the 10-bit adc output. these bits are undefined after a reset. the low bits are latched into this register whenever the adc data high byte register is read. [5:0] reserved these bits are reserved and must be programmed to 000000.
ps025113-1212 adc control register definitions z8 encore! ? f0830 series product specification 104 sample settling time register the sample settling time register, shown in table 66, is used to program a delay after the sample/hold signal is asserted and before the start signal is asserted; an adc conversion then begins. the number of cloc k cycles required fo r settling will vary from system to system depending on the system cl ock period used. the sy stem designer should program this register to contain the number of clocks required to meet a 0.5 s minimum settling time. table 66. sample settling time (adcsst) bit 7 6 5 4 3 2 1 0 field reserved sst reset 0 1111 r/w rr/w address f74h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3:0] ? sst 0h?fh = sample settling time in number of syst em clock periods to meet 0.5 s minimum.
ps025113-1212 adc control register definitions z8 encore! ? f0830 series product specification 105 sample time register the sample time register, shown in table 67, is used to program the length of active time for a sample after a conversion has begun by setting the start bit in the adc control register. the number of system clock cycles required for the sample time varies from sys- tem to system, depending on the clock period used. the system designer should program this register to contain the number of system clocks required to meet a 1 s minimum sam- ple time. table 67. sample time (adcst) bit 7 6 5 4 3 2 1 0 field reserved st reset 0 111111 r/w r/w r/w address f75h bit description [7:6] reserved these bits are reserved and must be programmed to 00. [5:0] ? st 0h?fh = sample-hold time in number of system clock periods to meet 1 s minimum.
ps025113-1212 comparator z8 encore! ? f0830 series product specification 106 comparator the z8 encore! f0830 series devices feature a general purpose comparator that compares two analog input signals. a gpio ( cinp ) pin provides the positive comparator input. the negative input ( cinn ) can be taken from either an extern al gpio pin or from an internal reference. the output is availabl e as an interrupt source or can be routed to an external pin using the gpio multiplex. the compar ator includes the following features: ? positive input is connected to a gpio pin ? negative input can be connecte d to either a gpio pin or a programmable internal ref- erence ? output can be either an interrupt sour ce or an output to an external pin operation one of the comparator inputs can be connecte d to an internal reference that is a user- selectable reference and is user-pr ogrammable with 200 mv resolution. the comparator can be powered down to save supply current. for details, see the power control register 0 section on page 31. as a result of the propagation delay of th e comparator, zilog does not recommend en- abling the comparator without first disablin g interrupts and waiting for the comparator output to settle. this delay prevents spur ious interrupts after comparator enabling. the following example shows how to safely enable the comparator: di ld cmp0,r0; load some new configuration nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei caution:
ps025113-1212 comparator control register definitions z8 encore! ? f0830 series product specification 107 comparator control register definitions the comparator control register (cmp0) co nfigures the comparator inputs and sets the value of the internal voltage reference. the gpio pin is always used as positive compara- tor input. table 68. comparator control register (cmp0) bit 7 6 5 4 3 2 1 0 field reserved innsel reflvl reserved reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f90h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? innsel signal select for negative input 0 = internal reference disabled, gpio pin used as negative comparator input. 1 = internal reference enabled as negative comparator input. [5:2] ? reflvl internal reference voltage level this reference is independent of the adc voltage reference. 0000 = 0.0 v. 0001 = 0.2 v. 0010 = 0.4 v. 0011 = 0.6 v. 0100 = 0.8 v. 0101 = 1.0 v (default). 0110 = 1.2 v. 0111 = 1.4 v. 1000 = 1.6 v. 1001 = 1.8 v. 1010?1111 = reserved. [1:0] reserved these bits are reserved and must be programmed to 00.
ps025113-1212 flash memory z8 encore! ? f0830 series product specification 108 flash memory the products in the z8 encore! f0830 seri es features either 1 kb (1024 bytes with nvds), 2 kb (2048 bytes with nvds), 4 kb (4096 bytes with nvds), 8 kb (8192 bytes with nvds) or 12 kb (12288 bytes with no nvds) of nonvolatile flash memory with read/write/erase capability. flash memory can be programmed and erased in-circuit by either user code or through the on-chip debugger. the flash memory array is a rranged in pages with 512 bytes per page. the 512-byte page is the minimum flash block size that can be er ased. each page is divided into eight rows of 64 bytes. for program/data protection, flash memory is also divided into sectors. in the z8 encore! f0830 series, each sector maps to one page (for 1 kb, 2 kb and 4 kb devices), two pages (8 kb device) or three pages (12 kb device). the first two bytes of flash program memory is used as flash option bits. for more infor- mation, see the flash option bits chapter on page 124. table 69 lists the flash memory configuratio n for each device in the z8 encore! f0830 series. figures 14 through 18 display the me mory arrangements fo r each flash memory size. table 69. z8 encore! f0830 series flash memory configuration part number flash size kb (bytes) flash pages program memory addresses flash sector size (bytes) z8f123x 12 (12,288) 24 0000h?2fffh 1536 z8f083x 8 (8196) 16 0000h?1fffh 1024 z8f043x 4 (4096) 8 0000h?0fffh 512 z8f023x 2 (2048) 4 0000h?07ffh 512 z8f013x 1 (1024) 2 0000h?03ffh 512 figure 14. 1k flash with nvds page 1 page 0 sector 1 sector 0 03ffh 0200h 01ffh 0000h 0200h 01ffh 03ffh 0000h
ps025113-1212 flash memory z8 encore! ? f0830 series product specification 109 figure 15. 2k flash with nvds figure 16. 4k flash with nvds page 3 page 2 page 1 page 0 sector 3 sector 2 sector 1 sector 0 07ffh 0600h 05ffh 0400h 03ffh 0200h 01ffh 0000h 07ffh 0600h 05ffh 0400h 03ffh 0200h 01ffh 0000h page 7 page 6 page 5 page 4 page 3 page 2 page 1 page 0 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 0fffh 0e00h 0dffh 0c00h 0bffh 0a00h 09ffh 0800h 07ffh 0600h 05ffh 0400h 03ffh 0200h 01ffh 0000h 0fffh 0e00h 0dffh 0c00h 0bffh 0a00h 09ffh 0800h 07ffh 0600h 05ffh 0400h 03ffh 0200h 01ffh 0000h
ps025113-1212 flash memory z8 encore! ? f0830 series product specification 110 figure 17. 8k flash with nvds sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 1fffh 1c00h 1bffh 1800h 17ffh 1fffh 1c00h 18ffh 1800h 17ffh 1400h 13ffh 1c00h 0fffh 0c00h 0bffh 0800h 07ffh 0400h 03ffh 0000h page 15 page 14 page 13 page 12 page 11 page 10 page 9 page 8 page 7 page 6 page 5 page 4 page 3 page 2 page 1 1e00h 1dffh 1a00h 19ffh 1600h 15ffh 1400h 13ffh 1200h 11ffh 1c00h 0fffh 0e00h 0dffh 0c00h 0bffh 0a00h 09ffh 0800h 07ffh 0600h 05ffh 0400h 03ffh 0200h 0100h 0000h page 0
ps025113-1212 data memory address space z8 encore! ? f0830 series product specification 111 data memory address space the flash information area, including zilog fl ash option bits, are located in the data mem- ory address space. the z8 encore! mcu is co nfigured by these proprietary flash option bits to prevent the user from writing to the ez8 cpu data memory address space. flash information area the flash information area is physically separate from progra m memory and is mapped to the address range fe00h to fe7fh . not all of these addresses are user-accessible. factory trim values for the vbo, internal precision oscillator and factory calibration data for the adc are stored here. table 70 describes the flash information area . this 128-byte information area is accessed by setting the bit 7 of the flash page select register to 1. when access is enabled, the figure 18. 12k flash without nvds 2fffh sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 page 20 page 21 page 22 page 23 05ffh page 0 page 1 page 2 03ffh 0200h 0400h 01ffh 0000h 2e00h 2dffh 2c00h 2bffh 2a00h 2fffh 2a00h 29ffh 1600h 23ffh 1e00h 1dffh 1800h 17ffh 1200h 11ffh 0c00h 0bffh 0600h 05ffh 0000h
ps025113-1212 operation z8 encore! ? f0830 series product specification 112 flash information area is mapp ed into program memory and overlays the 128 bytes in the address range fe00h to fe7fh . when the information area access is enabled, all reads from these program memory addresses return the information area data rather than the program memory data. access to the flash information area is read-only. the trim bits are handled differently than the other zilog flash option bits. the trim bits are the hybrid of the user option bits and th e standard zilog option bits. these trim bits must be user-accessible for reading at all times using external registers regardless of the state of bit 7 in the flash page select register . writes to the trim space change the value of the option bit holding register but do not affe ct the flash bits, which remain as read- only. operation the flash controller programs and erases fl ash memory. the flash controller provides the proper flash controls and timing for byte programming, page erase and mass erase of flash memory. the flash controller contains several protec tion mechanisms to prevent accidental pro- gramming or erasure. these mechanism operat e on the page, sector and full-memory lev- els. the flowchart in figure 19 display basic fl ash controller operatio n. the following sub- sections provide details about the various operations (lock, unlock, byte programming, page protect, page unprotect, page select page erase and mass erase) displayed in figure 19. table 70. z8f083 flash memory area map program memory address (hex) function fe00?fe3f zilog option bits fe40?fe53 part number 20-character ascii alphanumeric code left justified and filled with fh fe54?fe5f reserved fe60?fe7f reserved
ps025113-1212 operation z8 encore! ? f0830 series product specification 113 figure 19. flash controller operation flow chart reset page 73h no yes 8ch no yes program/erase enabled 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program page erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes
ps025113-1212 operation z8 encore! ? f0830 series product specification 114 flash operation timing using the flash freq uency registers before performing either a program or erase operation on flash memory, the user must first configure the flash frequency high an d low byte registers. the flash frequency registers allow programming and erasing of the flash with system clock frequencies rang- ing from 10 khz to 20 mhz. the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control the timing for flash program and erase operations. the 16-bit binary flash fre- quency value must contain the system clock frequency (in khz). this value is calculated using the following equation: flash programming and erasure are not supp orted for system clock frequencies below 10 khz or above 20 mhz. the flash frequency high and low byte registers must be loaded with the correct value to ensure oper ation of the z8 encore! f0830 series devices. flash code protection against external access the user code contained within flash memory can be protected against external access by using the on-chip debugger. programming the frp flash option bit prevents reading of the user code using the on-chip debugger. for more information, see the flash option bits chapter on page 124 and the on-chip debugger chapter on page 139. flash code protection agai nst accidental program and erasure the z8 encore! f0830 series prov ides several levels of prot ection against accidental pro- gram and erasure of the flash memory contents . this protection is provided by a combina- tion of the flash option bits, th e register locking mechanism, the page select redundancy and the sector level protection co ntrol of the flash controller. flash code protection us ing the flash option bits the fhswp and fwp flash option bits combine to provide three levels of flash program memory protection, as listed in table 71. see the flash option bits chapter on page 124 for more information. ffreq[15:0] system clock frequency (hz) 1000 ------------------------------------------------------------------------ = caution:
ps025113-1212 operation z8 encore! ? f0830 series product specification 115 at reset, the flash controller is locked to prevent accidental program or erasure of flash memory. to program or erase flash memory, first write the target page to the page select register. unlock the flash controller by maki ng two consecutive writes to the flash con- trol register with the values 73h and 8ch , sequentially. the page select register must be rewritten with the same page previously stored there. if the two page select writes do not match, the controller reverts to a locked state. if the two writes match, the selected page becomes active. see fi gure 19 for details. after unlocking a specific page , you can enable either page program or erase. writing the value 95h causes a page erase only if the active page resides in a sector that is not pro- tected. any other value written to the flash co ntrol register locks the flash controller. mass erase is not allowed in the user code , but is allowed thro ugh the debug port. after unlocking a specific page , the user can also write to any byte on that page. after a byte is written, the page remains unlocked, a llowing for subsequent writes to other bytes on the same page. further writes to the flas h control register causes the active page to revert to a locked state. sector based flash protection the final protection mechanism is implemente d on a per-sector basis. the flash memories of z8 encore! devices are divided into maximu m number of eight sectors. a sector is one- eighth of the total size of flash memory, unless this value is smaller than the page size, in which case the sector and page sizes are equal. on z8 encore! f0830 series devices, the sector size is varied according to the z8 encore! f0830 series fl ash memory configura- tion shown in table 69 on page 108 and in figures 14 through 18, which follow the table the flash sector protect register can be co nfigured to prevent sectors from being pro- grammed or erased. after a sector is protected, it cannot be unprotected by user code. the flash sector protect register is cleared af ter reset and any previously written protection values is lost. user co de must write this register in thei r initialization routine if they want to enable sector protection. the flash sector protect register shares its register file address with the page select register. the flash sector protect register is accessed by writing the flash control regis- ter with 5eh . after the flash sector protect register is selected, it can be accessed at the page select register address. when user code writes the flash sector protect register, table 71. flash code protection using the flash option bits fhswp fwp flash code protection description 0 0 programming and erasing disabled for all flash program memory. in user code pro- gramming, page erase and mass erase are all disabled. mass erase is available through the on-chip debugger. 0 or 1 1 programming, page erase and mass erase are enabled for all of the flash program memory.
ps025113-1212 operation z8 encore! ? f0830 series product specification 116 bits can only be set to 1. thus, sectors can be protected, but not unprotected, via register write operations. writing a value other than 5eh to the flash control register deselects the flash sector protect register and reen ables access to the page select register. observe the following procedure to setup th e flash sector protect register from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write 5eh to the flash control register to select the flash sector protect register. 3. read and/or write the flash sector protect register which is now at register file address ff9h . 4. write 00h to the flash control register to return the flash controller to its reset state. ? the sector protect register is initialized to 0 on reset, putting each sector into an unpro- tected state. when a bit in the sector protec t register is written to 1, the corresponding sector can no longer be written or erased. afte r setting a bit in the sector protect register, the bit cannot be cleared by the user. byte programming flash memory is enabled for byte programming after unlock ing the flash controller and successfully enabling either mass erase or page erase. when the flash controller is unlocked and mass erase is successfully enab led, all of the program memory locations are available for byte programming. in contrast , when the flash controller is unlocked and page erase is successfully enabled, only the locations of the selected page are available for byte programming. an erased flash byte contains all 1?s ( ff h ). the programming opera- tion can only be used to change bits from 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of either the page erase or mass erase commands. byte programming can be accomplished using the on-chip debugger?s write memory command or ez8 cpu execution of the ldc or ldci instructions. refer to the ez8 cpu core user manual (um0128) , which is available for download on w ww.zilog.com , for the description of the ldc and ldci instructions. while the flash controller programs the flash memory, the ez8 cpu idles, but the syst em clock and on-chip peripherals continue to operate. to exit programming mode and lo ck the flash, write any value to the flash control register, except the mass erase or page erase commands. the byte at each address w ithin flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. caution:
ps025113-1212 operation z8 encore! ? f0830 series product specification 117 page erase flash memory can be erased on e page (512 bytes) at a time. page erasing flash memory sets all bytes in that page to the value ffh . the flash page select register identifies the page to be erased. only a page residing in an unprotected sector can be erased. with the flash controller unlocked and the active page set, writing the value 95h to the flash con- trol register initiates the page erase oper ation. while the flash controller executes the page erase operation, the ez8 cpu idles, bu t the system clock and on-chip peripherals continue to operate. the ez 8 cpu resumes operation after the page erase operation com- pletes. if the page erase operation is performed using the on-chip debugger, poll the flash status register to determine when th e page erase operation is complete. when the page erase is complete, the flash controller returns to its locked state. mass erase flash memory can also be mass erased using the flash controller, bu t only by using the on-chip debugger. mass erasing flash memory sets all bytes to the value ffh . with the flash controller unlocked an d the mass erase successfully enabled, writing the value 63h to the flash control register initiates the mass erase operation. while the flash control- ler executes the mass erase operation, the ez 8 cpu idles, but the system clock and on- chip peripherals continue to operate. using the on-chip debugger, poll the flash status register to determine when the mass erase operation is complete. when the mass erase is complete, the flash controller returns to its locked state. flash controller bypass the flash controller can be bypassed; instead , the control signals for flash memory can be brought out to the gpio pins. bypassing the flash controller allows faster row pro- gramming algorithms by controlling th e flash programming signals directly. row programing is recommended for gang programming applications and large volume customers who do not require in-circuit initia l programming of flash memory. mass erase and page erase operations are also supporte d, when the flash controller is bypassed. for more information ab out bypassing the flash controller, refer to third-party flash programming support for z8 encore! . this document is avai lable for download at www.zilog.com . flash controller behavior in debug mode the following behavioral changes can be obse rved in the flash cont roller when the flash controller is accessed us ing the on-chip debugger: ? the flash write protect option bit is ignored.
ps025113-1212 nvds operational requirements z8 encore! ? f0830 series product specification 118 ? the flash sector protect register is ignored for programming and erase operations. ? programming operations are no t limited to the page selected in the page select register. ? bits in the flash sector protect register can be written to one or zero. ? the second write of the page select regist er to unlock the flash controller is not necessary. ? the page select register can be written when the flash controller is unlocked. ? the mass erase command is enabled through the flash control register for security reasons, flash controller allows on ly a single page to be opened for write/ erase. when writing multiple flash pages, the flash controller must go through the un- lock sequence again to select another page. nvds operational requirements the device uses a 12 kb flash memory space, despite the maximum specified flash size of 8 kb (with the exception of 12 kb mode with non-nvds). user code accesses the lower 8 kb of flash, leaving the upper 4 kb for proprietary (for zilog-only) memory. the nvds is implemented by using this propri etary memory space for special-purpose rou- tines and for the data required by these ro utines, which are factor y-programmed and can- not be altered by the user. the nvds operation is described in detail in the nonvolatile data storage chapter on page 134. the nvds routines are triggered by a user code: call into proprietary memory. code executing from this proprietary memory must be able to read and write other locations within proprietary memory. user code must no t be able to read or write proprietary mem- ory. flash control register definitions this section defines the features of the following flash control registers. flash control register : see page 119 flash status register : see page 120 flash page select register : see page 121 flash sector protect register : see page 122 flash frequency high and low byte registers : see page 123 caution:
ps025113-1212 flash control register definitions z8 encore! ? f0830 series product specification 119 flash control register the flash controller must be unlocked usin g the flash control register before program- ming or erasing flash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the flash controller. when the flash controller is unlocked, flash memory can be enabled for mass erase or page erase by writing the appropriate enable command to the fctl. page erase applie s only to the active page selected in flash page select register. mass erase is enable d only through the on-chip debugger. writing an invalid value or an invali d sequence returns the flash cont roller to its locked state. the write-only flash control register shares its register file address with the read-only flash status register. table 72. flash control register (fctl) bit 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww address ff8h bit description [7:0] ? fcmd flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command (must be third command in sequence to initiate page erase). 63h = mass erase command (must be third command in sequence to initiate mass erase). 5eh = enable flash sector protect register access.
ps025113-1212 flash control register definitions z8 encore! ? f0830 series product specification 120 flash status register the flash status register indicates the current state of the flash controller. this register can be read at any time. the read-only flash st atus register shares its register file address with the write-only flash control register. table 73. flash status register (fstat) bit 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr address ff8h bit description [7:6] reserved these bits are reserved and must be programmed to 00. [5:0] ? fstat flash controller status 000000 = flash controller locked. 000001 = first unlock command received (73h written). 000010 = second unlock command received (8ch written). 000011 = flash controller unlocked. 000100 = sector protect register selected. 001xxx = program operation in progress. 010xxx = page erase operation in progress. 100xxx = mass erase operation in progress.
ps025113-1212 flash control register definitions z8 encore! ? f0830 series product specification 121 flash page select register the flash page select register shares address space with the flash sector protect regis- ter. unless the flash controller is locked and written with 5eh , any writes to this address will target the flash page select register. the register selects one of the eight available flash memory pages to be programmed or erased. each flash page contains 512-bytes of flash memory. during a page erase opera- tion, all flash memory contai ning addresses with the most significant 7-bits within fps[6:0] are chosen for program/erase operations. table 74. flash page select register (fps) bit 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h bit description [7] ? info_en information area enable 0 = information area is not selected. 1 = information area is selected. the information area is mapped into the program memory address space at addresses fe00h through ffffh . [6:0] ? page page select this 7-bit field identifies the flash memory page for page erase and page unlocking. program memory address[15:9] = page[6:0]. for z8f04xx and z8f02xx devices, the upper four bits must always be 0. for z8f0 1xx devices, the upper five bits must always be 0.
ps025113-1212 flash control register definitions z8 encore! ? f0830 series product specification 122 flash sector protect register the flash sector protect register is shared w ith the flash page select register. when the flash control register is locked and written with 5eh , the next write to this address tar- gets the flash sector protect register. in all other cases, it targets the flash page select register. this register selects one of the eight availa ble flash memory sectors to be protected. the reset state of each sector protect bit is the ze ro (unprotected) state. after a sector is pro- tected by setting its corresponding register bit, the register bit cannot be cleared by the user. to determine the appropriate flash memory sector address range and sector number for your f0830 series product, please refer to table 70 on page 112. table 75. flash sector protect register (fprot) bit 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h bit description [7:0] ? sprot x sector protection for z8f12xx, z8f08xx and z8f04xx devices, all bits are used. for z8f02xx devices, the upper four bits remain unused. for z8f01xx de vices, the upper six bits remain unused. to determine the appropriate flash memory sector address range and sector number for your f0830 series product, please refer to table 69 and to figures 14 through 18. note: x indicates bits in the range 7?0.
ps025113-1212 flash control register definitions z8 encore! ? f0830 series product specification 123 flash frequency high and low byte registers the flash frequency high and low byte regi sters, shown in tables 76 and 77, combine to form a 16-bit value, ffreq, to control ti ming for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated usin g the following equation: flash programming and erasure is not supporte d for system clock frequencies below 10 khz or above 20 mhz. the flash frequency high and low byte registers must be loaded with the correct value to ensu re proper operation of the device. table 76. flash frequency high byte register (ffreqh) bit 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ffah bit description [7:0] ? ffreqh flash frequency high byte high byte of the 16-bit flash frequency value. table 77. flash frequency low byte register (ffreql) bit 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w address ffbh bit description [7:0] ? ffreql flash frequency high byte low byte of the 16-bit flash frequency value. ffreq[15:0] ffreqh[7:0],ffreql[7:0] ?? system clock frequency 1000 ----------------------------------------------------------- - == caution:
ps025113-1212 flash option bits z8 encore! ? f0830 series product specification 124 flash option bits programmable flash option bits allow user co nfiguration of certain aspects of z8 encore! f0830 series operation. the feature configura tion data is stored in the flash program memory and read during reset . the features available for co ntrol through the flash option bits are: ? watchdog timer time-out response selection?interrupt or system reset ? watchdog timer enabled at reset ? the ability to prevent unwa nted read access to user code in program memory ? the ability to prevent accidental programming and erasure of all or a portion of the user code in program memory ? voltage brown-out configuration always enab led or disabled during stop mode to re- duce stop mode power consumption ? oscillator mode selection for high, medium and low power crystal oscillators or external rc oscillator ? factory trimming information for the inte rnal precision oscillator and vbo voltage operation this section describes the type and configur ation of the programmable flash option bits. option bit configuration by reset each time the flash option bits are programmed or erased, the device must be reset for the change to be effective. during any reset operation (system reset or stop mode recovery), the flash option bits are automa tically read from flash progra m memory and written to the option configuration registers, which control z8 encore! f0830 series device operation. option bit control is establishe d before the device exits reset and the ez8 cpu begins code execution. the option configuration registers are not part of the register file and are not accessible for read or write access.
ps025113-1212 operation z8 encore! ? f0830 series product specification 125 option bit types this section describes the two types of flas h option bits offered in the f0830 series. user option bits the user option bits are contained in the first two bytes of program memory. user access to these bits is provided be cause these locations contain app lication specific device config- urations. the information contained here is lost when page 0 of program memory is erased. trim option bits the trim option bits are contained in the info rmation page of the flash memory. these bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanently altered by the user. program memory can be erased without endangering these values. it is possible to alter work ing values of these bits by accessing the trim bit address and data register s, but these working values are lost after a power loss. there are 32 bytes of trim data. to modify on e of these values, the user code must first write a value between 00h and 1fh into the trim bit address register. the next write to the trim bit data register changes the working value of the target trim data byte. reading the trim data requires the u ser code to write a value between 00h and 1fh into the trim bit address register. the next read fro m the trim bit data register returns the working value of the target trim data byte. the trim address range is from information address 20?3f only. the remaining informa- tion page is not accessible via the trim bit address and data registers. during reset, the first 43 system clock cycles perform 43 flash accesses. the six bits of the counter provide the lower six bits of the flash memory address. all other address bits are set to 0. the option bit registers use th e 6-bit address from the counter as an address and latch the data from the fl ash on the positive edge of th e ipo clock, allowing for a maximum of 344-bits (43 bytes) of op tion information to be read from flash. because option information is stored in both th e first two bytes of program memory and in the information area of flash memory, the data must be placed in specific locations to be read correctly. in this case, the first two bytes at addresses 0 and 1 in program memory are read out and the remainder of the bytes ar e read out of the flash information area. note:
ps025113-1212 flash option bit control register definitions z8 encore! ? f0830 series product specification 126 flash option bit control register definitions this section briefly describes the features of the trim bit address and data registers. trim bit address register the trim bit address register, shown in tabl e 78, contains the target address to access the trim option bits. trim bit addresses in the range 00h?1fh map to the information area at addresses 20h?3fh , as shown in table 79. trim bit data register the trim bit data register, shown in table 80 , contains the read or write data to access the trim option bits. table 78. trim bit address register (trmadr) bit 7 6 5 4 3 2 1 0 field trmadr: trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff6h table 79. trim bit address map trim bit address information area address 00h 20h 01h 21h 02h 22h 03h 23h :: 1fh 3fh
ps025113-1212 flash option bit address space z8 encore! ? f0830 series product specification 127 flash option bit address space the first two bytes of flash program memory at addresses 0000h and 0001h are reserved for the user-programmable flash option bits. see tables 81 and 82. table 80. trim bit data register (trmdr) bit 7 6 5 4 3 2 1 0 field trmdr: trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff7h table 81. flash option bits at program memory address 0000h bit 7 6 5 4 3 2 1 0 field wdt_res wdt_ao osc_sel[1:0] vbo_ao frp reserved fwp reset u uuuuuuu r/w r/w r/w r/w r/w r/w r/w r/w r/w address program memory 0000h note: u = unchanged by reset. r/w = read/write. bit description [7] ? wdt_res watchdog timer reset 0 = watchdog timer time-out generates an inte rrupt request. in terrupts must be globally enabled for the ez8 cpu to acknowledge the interrupt request. 1 = watchdog timer time-out causes a system re set. this is the default setting for unpro- grammed (erased) flash. [6] ? wdt_ao watchdog timer always on 0 = on application of system power, watchdo g timer is automatically enabled. watchdog timer cannot be disabled. 1 = watchdog timer is enabled on execution of the wdt instruction. once enabled, the watchdog timer can only be disabled by a re set. this is the default setting for unpro- grammed (erased) flash. [5:4] ? osc_sel oscillator mode selection 00 = on-chip oscillator configured for us e with external rc networks (<4 mhz). 01 = minimum power for use with very low frequency crystals (32 khz to 1.0 mhz). 10 = medium power for use with medium frequency crystals or ceramic resonators (0.5 mhz to 5.0 mhz). 11 = maximum power for use with high frequency crystals (5.0 mhz to 20.0 mhz). this is the default setting for unprogrammed (erased) flash.
ps025113-1212 flash option bit address space z8 encore! ? f0830 series product specification 128 [3] ? vbo_ao voltage brown-out protection always on 0 = voltage brown-out protection is disabled in stop mode to reduce total power con- sumption. 1 = voltage brown-out protection is always enabled, even during stop mode. this setting is the default setting for unprogrammed (erased) flash. [2] ? frp flash read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this is the default setting for un programmed (erased) flash. [1] reserved this bit is reserved and must be programmed to 1. [0] ? fwp flash write protect this option bit provides fl ash program memory protection. 0 = programming and erasure disabled for a ll flash program memory. programming, page erase and mass erase through user code is disa bled. mass erase is available using the on-chip debugger. 1 = programming, page erase and mass erase are enabled for all flash program memory. table 82. flash options bits at program memory address 0001h bit 7 6 5 4 3 2 1 0 field vbo_res reserved xtldis reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address program memory 0001h note: u = unchanged by reset. r/w = read/write. bit description [7] ? vbo_res voltage brown-out reset 1 = vbo detection causes a system reset. this setting is the default setting for unpro- grammed (erased) flash. [6:5] reserved these bits are reserved and must be programmed to 11. bit description (continued)
ps025113-1212 trim bit address space z8 encore! ? f0830 series product specification 129 trim bit address space all available trim bit addresses and their func tions are listed in tables 83 through 90. [4] ? xtldis state of the crystal oscillator at reset this bit enables only the crystal oscillator. selecting the crystal o scillator as the system clock must be performed manually. 0 = the crystal oscillator is enabled during reset, resulting in lo nger reset timing. 1 = the crystal oscillator is disabled during reset, resulting in shorter reset timing. [3:0] reserved these bits are reserved and must be programmed to 1111. bit description (continued)
ps025113-1212 trim bit address space z8 encore! ? f0830 series product specification 130 the bit values used in table 84 are set at the factory; no calibration is required. table 83. trim bit address space address function 00h adc reference voltage 01h adc and comparator 02h internal precision oscillator 03h oscillator and vbo 06h clkfltr table 84. trim option bits at 0000h (adcref) bit 7 6 5 4 3 2 1 0 field adcref_trim reserved reset uu r/w r/w r/w address information page memory 0020h note: u = unchanged by reset. r/w = read/write. bit description [7:3] ? adcref_trim adc reference voltage trim byte contains trimming bits for adc reference voltage. [2:0] reserved these bits are reserved and must be programmed to 111. table 85. trim option bits at 0001h (tadc_comp) bit 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0021h note: u = unchanged by reset. r/w = read/write. bit description [7:0] reserved altering this register may result in incorrect device operation. note:
ps025113-1212 trim bit address space z8 encore! ? f0830 series product specification 131 the bit values used in table 85 are set at the factory; no calibration is required. the bit values used in table 86 are set at the factory; no calibration is required. table 86. trim option bits at 0002h (tipo) bit 7 6 5 4 3 2 1 0 field ipo_trim reset u r/w r/w address information page memory 0022h note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? ipo_trim internal precision oscillator trim byte contains trimming bits for th e internal precision oscillator. table 87. trim option bits at 0003h (tvbo) bit 7 6 5 4 3 2 1 0 field reserved reserved vbo_trim reset u u100 r/w r/w r/w r/w address information page memory 0023h note: u = unchanged by reset. r/w = read/write. bit description [7:3] reserved these bits are reserved and must be programmed to 11111. [2] ? vbo_trim vbo trim values contains factory-trimmed values for the oscillator and the vbo. note: note:
ps025113-1212 trim bit address space z8 encore! ? f0830 series product specification 132 the bit values used in table 87 are set at the factory; no calibration is required. on-chip flash memory is only guaranteed to perform write operations when voltage sup- plies exceed 2.7 v. write operations at voltages below 2.7 v will yield unpredictable results. table 88. vbo trim definition vbo_trim trigger voltage level 000 1.7 001 1.6 101 2.2 110 2.0 100 2.4 111 1.8 table 89. trim option bits at 0006h (tclkflt) bit 7 6 5 4 3 2 1 0 field divby4 reserved dlyctl1 dlyctl2 dlyct l3 reserved filter sel1 filtersel0 reset 01000100 r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0026h note: u = unchanged by reset. r/w = read/write. bit description [7] ? divby4 output frequency selection 0 = output frequency is input frequency. 1 = output frequency is 1/4 of the input frequency. [6] reserved this bit is reserved and must be programmed to 1. [5:3] ? dlyctl x delay control 3-bit selection for the pulse width that can be filt ered. see table 90 for delay control values at 3.3 v operation voltage. [2] reserved this bit is reserved and must be programmed to 1. notes: x indicates bit values 3?1; y indicates bit values 1?0. note:
ps025113-1212 trim bit address space z8 encore! ? f0830 series product specification 133 the bit values used in table 89 are set at factory and no calibration is required. [1:0] ? filtersel y filter select 2-bit selection for the clock filter mode. 00 = no filter. 01 = filter low level no ise on high level signal. 10 = filter high level no ise on low level signal. 11 = filter both. table 90. clkflt del ay control definition dlyctl3, dlyctl2, dlyctl1 low noise pulse on high signal (ns) high noise pulse on low signal (ns) 000 5 5 001 7 7 010 9 9 011 11 11 100 13 13 101 17 17 110 20 20 111 25 25 note: the variation is about 30%. bit description (continued) notes: x indicates bit values 3?1; y indicates bit values 1?0. note:
ps025113-1212 nonvolatile data storage z8 encore! ? f0830 series product specification 134 nonvolatile data storage z8 encore! f0830 series devices contain a no nvolatile data storage (nvds) element of up to 64 bytes (except when in flash 12 kb mode). this type of memory can perform over 100,000 write cycles. operation nvds is implemented by special-purpose zilog software stored in areas of program mem- ory that are not user-accessible. these special- purpose routines use flash memory to store the data, and incorporate a dynamic addressing scheme to maximize the write/erase endur- ance of the flash. the products in the z8 encore! f0830 series feature multiple nvds array sizes. see the z8 encore! f0830 series fa mily part selection guide section on page 2 for details. nvds code interface two routines are required to access the nvds: a write routine and a read routine. both of these routines are accessed with a call instruction to a predefined address outside of pro- gram memory that is accessible to the user. both the nvds address and data are single- byte values. in order to not disturb the user code, these routines save the working register set before using it so that 16 bytes of stac k space are required to preserve the site. after finishing the call to these routin es, the working register set of the user code is recovered. during both read and write accesses to the nvds , interrupt service is not disabled. any interrupts that occur during nvds execution must not disturb the working register and existing stack contents; otherw ise, the array can become corrupted. zilog recommends the user disable interrupts before executing nvds operations. use of the nvds requires 16 bytes of available stack space. the contents of the working register set are saved before calling nvds read or write routines. for correct nvds operation, the flash frequency registers must be programmed based on the system clock frequency. see the flash operation timing using the flash frequency registers section on page 114 . note:
ps025113-1212 nvds code interface z8 encore! ? f0830 series product specification 135 byte write to write a byte to the nvds array, the user code must first push the ad dress, then the data byte onto the stack. th e user code issues a call instruction to the address of the byte write routine ( 0x20b3 ). at the return from the subroutine , the write status byte resides in working register r0. the bit fields of this st atus byte are defined in table 91. additionally, user code should pop the address and data bytes off the stack. the write routine uses 16 bytes of stack space in addition to the two bytes of address and data pushed by the user code. sufficient me mory must be available for this stack usage. because of the flash memory architecture, nv ds writes exhibit a nonuniform execution time. in general, a write takes 136 s (assu ming a 20 mhz system clock). for every 200 writes, however, a maintenance operation is n ecessary. in this rare occurrence, the write takes up to 58 ms to complete . slower system clock speeds result in proportionally higher execution times. nvds byte writes to invalid addresses (those exceeding the nvds array size) have no effect. illegal write operations have a 7 s execution time. table 91. write status byte bit 7 6 5 4 3 2 1 0 field reserved fe igaddr we default value 00000000 bit description [7:3] reserved these bits are reserved and must be programmed to 00000. [2] ? fe flash error if a flash error is detected, this bit is set to 1. [1] ? igaddr illegal address when an nvds byte writes to invalid addresses occur (those exceeding the nvds array size), this bit is set to 1. [0] ? we write error a failure occurs during data writes to flash. w hen writing data into a certain address, a read- back operation is performed. if the read-back value is not the same as the value written, this bit is set to 1.
ps025113-1212 nvds code interface z8 encore! ? f0830 series product specification 136 byte read to read a byte from the nvds array, user co de must first push the address onto the stack. user code issues a call instruction to the address of the byte-read routine ( 0x2000 ). at the return from the subroutine, the read byte resides in work ing register r0 and the read status byte resides in working register r1. the bit fields of this status byte are defined in table 92. additionally, the user code shou ld pop the address byte off the stack. the read routine uses 16 bytes of stack space in addition to the one byte of address pushed by the user code. sufficient memory mu st be available for this stack usage. due to the flash memory arch itecture, nvds reads exhibit a nonuniform execution time. a read operation takes between 71 s and 258 s (assuming a 20 mhz system clock). slower system clock speeds result in proportionally higher execution times. nvds byte reads from invalid addresses (those exceeding the nvds array size) return 0xff . illegal read operations have a 6 s execution time. the status byte returned by the nvds read routine is zero for a successful read. if the sta- tus byte is nonzero, there is a corrupted value in the nvds array at the location being read. in this case, the value returned in r0 is the byte most recently written to the array that does not have an error. table 92. read status byte bit 7 6 5 4 3 2 1 0 field reserved de reserved fe igaddr reserved default value 00000000 bit description [7:5] reserved these bits are reserved and must be programmed to 000. [4] ? de data error when reading an nvds address, if an error is found in the latest data corresponding to this nvds address, this bit is set to 1. nvds source code step s forward until it finds valid data at this address. [3] reserved this bit is reserved and must be programmed to 0. [2] ? fe flash error if a flash error is detected, this bit is set to 1. [1] ? igaddr illegal address when nvds byte reads from invalid addresses (those exceeding the nvds array size) occur, this bit is set to 1. [0] reserved this bit is reserved and must be programmed to 0.
ps025113-1212 nvds code interface z8 encore! ? f0830 series product specification 137 power failure protection nvds routines employ error-chec king mechanisms to ensure that any power failure will only endanger the most recently written byte. bytes previously written to the array are not perturbed. for this protection to functi on, the vbo must be enabled (see the low-power modes chapter on page 30) and configured for a threshold voltage of 2.4 v or greater (see the trim bit address space section on page 129 ). a system reset (such as a pin reset or watchdog timer reset) that occurs during a write operation also perturbs the byt e currently being written. all other bytes in the array are unperturbed. optimizing nvds memory usage for execution speed as indicated in table 93, the nvds read time varies drastically; this discrepancy being a trade-off for minimizing the frequency of write s that require post-write page erases. the nvds read time of address n is a function of the number of writes to addresses other than n since the most recent write to address n as we ll as the number of writes since the most recent page erase. neglecting the effects caused by page erases and results caused by the initial condition in which the nvds is blank, a rule of thumb to consider is that every write since the most recent page erase causes read times of unwritten addresses to increase by 0.8 s up to a maximum of 258 s. for every 200 writes, a maintenance operation is necessary. in this rare occurrence, the write takes up to 58 ms to complete. if nvds read performance is critical to your software architecture, you can optimize your code for speed by using either of the two methods listed below. 1. periodically refresh all addresses that are used; this is the more useful method. the optimal use of nvds, in terms of speed, is to rotate the writes evenly among all addresses planned for use, thereby bringing all reads closer to the minimum read time. table 93. nvds read time operation minimum latency (s) maximum latency (s) read 71 258 write 126 136 illegal read 6 6 illegal write 7 7 note:
ps025113-1212 nvds code interface z8 encore! ? f0830 series product specification 138 because the minimum read time is much less than the write time, however, actual speed benefits are not always realized. 2. use as few unique addresses as possible to optimize the impact of refreshing.
ps025113-1212 on-chip debugger z8 encore! ? f0830 series product specification 139 on-chip debugger the z8 encore! devices contain an integrated on-chip debugger (ocd) that provides the following advanced debugging features: ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints and watchpoints ? executing ez8 cpu instructions architecture the on-chip debugger consists of four primary functional blocks: transmitter, receiver, autobaud detector/generator and debug controller. figure 20 displays the architecture of the on-chip debugger. figure 20. on-chip debugger block diagram autobaud system clock transmitter receiver dbg pin debug controller ez8 cpu control detector/generator
ps025113-1212 operation z8 encore! ? f0830 series product specification 140 operation the following section descr ibes the operation of the on-chip debugging function. ocd interface the on-chip debugger uses the dbg pin for communication with an external host. this one-pin interface is a bidirec tional open-drain interface that transmits and receives data. data transmission is half-dup lex, which means that transmi ssion and data retrieval cannot occur simultaneously. the serial data on the dbg pin is sent using the standard asynchro- nous data format defined in rs-232.this pi n creates an interface between the z8 encore! f0830 series products and the serial port of a host pc using minima l external hardware. two different methods for connecting the dbg pi n to an rs-232 interface are displayed in figures 21 and 22. the recommended method is the buffered implementation depicted in figure 22. the dbg pin must always be connected to v dd through an external pull-up resistor. for proper operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must always be connected to v dd through an external pull- up resistor to ensure proper operation. figure 21. interfacing the on-chip debugger?s dbg pin with an rs-232 interface, #1 of 2 caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10k ? schottky diode
ps025113-1212 operation z8 encore! ? f0830 series product specification 141 debug mode the operating characteristics of the devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez8 cpu, unless directed by the ocd to ex- ecute specific instructions ? the system clock operates, unless the device is in stop mode ? all enabled on-chip peripherals operate, unless the device is in stop mode ? automatically exits halt mode ? constantly refreshes the wa tchdog timer, if enabled entering debug mode ? the device enters debug mode after the ez8 cpu executes a breakpoint (brk) in- struction ? if the dbg pin is held low during the most recent clock cycle of system reset, the de- vice enters debug mode on exiting system reset exiting debug mode the device exits debug mode foll owing any of these operations: ? clearing the dbgmode bit in th e ocd control register to 0 ? power-on reset ? voltage brown-out reset figure 22. interfacing the on-chip debugger?s dbg pin with an rs-232 interface, #2 of 2 rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10k ? open-drain buffer
ps025113-1212 operation z8 encore! ? f0830 series product specification 142 ? watchdog timer reset ? asserting the reset pin low to initiate a reset ? driving the dbg pin low while the device is in stop mode initia tes a system reset ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (least -significant bit first) and 1 stop bit. see figure 23. ocd autobaud detector/generator to run over a range of baud rates (data bits per second) with various system clock frequen- cies, the on-chip debugger contains an auto baud detector/generator. after a reset, the ocd is idle until it receives data. the ocd re quires that the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits), framed between high bits . the autobaud detector measures this period and sets the ocd baud rate generator accordingly. the autobaud detector/generator is clocked by the system clock. the minimum baud rate is the system clock frequency divided by 51 2. for optimal operation with asynchronous datastreams, the maximum recommended baud ra te is the system clock frequency divided by 8. the maximum possible baud rate for as ynchronous datastreams is the system clock frequency divided by 4, but this theoretica l maximum is possible only for low noise designs with clean signals. table 94 lists minimum and recommended maximum baud rates for sample crystal frequencies. figure 23. ocd data format table 94. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 20.0 2500.0 1,843,200 39 1.0 125.0 115,200 1.95 0.032768 (32 khz) 4.096 2400 0.064 startd0d1d2d3d4d5d6d7stop
ps025113-1212 operation z8 encore! ? f0830 series product specification 143 if the ocd receives a serial break (nine or more continuous bits low), the autobaud detec- tor/generator resets. reconf igure the autobaud detect or/generator by sending 80h . ocd serial errors the ocd can detect any of the following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (simultaneou s transmission by ocd and host detected by the ocd) ? when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial break back to the host and resets the autobaud detec- tor/generator. a framing error or transmit co llision may be caused by the host sending a serial break to the ocd. as a result of the ope n-drain nature of the interface, returning a serial break back to the host only extends the length of the serial break if the host releases the serial break early. the host transmits a serial break on the dbg pin when first connecting to the z8 encore! f0830 series devices or when recovering from an error. a serial break from the host resets the autobaud generator/detector, but does no t reset the ocd control register. a serial break leaves the device in debu g mode, if that is the current mode. the ocd is held in reset until the end of the serial break when th e dbg pin returns high. because of the open- drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. breakpoints execution breakpoints ar e generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signal s the ocd. if breakpoints are enabled, the ocd enters debug mode and idles the ez8 cpu. if breakpoints are not enabled, the ocd ignores the brk signal and the brk instruction operates as an nop instruction. breakpoints in flash memory the brk instruction is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to im plement a breakpoint, write 00h to the required break address overwriting the current instruction. to remo ve a breakpoint, the corresponding page of flash memory must be erased and re programmed with the original data.
ps025113-1212 on-chip debugger commands z8 encore! ? f0830 series product specification 144 runtime counter the ocd contains a 16-bit runtime counter. it counts system clock cycles between break- points. the counter starts counting when the ocd leaves debug mode and stops count- ing when it enters debug mode again or when it reaches the maximum count of ffffh . on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation, on ly a subset of the ocd commands are avail- able. in debug mode, all ocd commands be come available unless the user code and control registers are protected by programming the flash read protect option bit (frp). the frp prevents the code in memory from being read out of the z8 encore! f0830 series products. when this option is enabled, se veral of the ocd commands are disabled. table 95 summarizes the on-chip debugger commands. this tabl e indicates the com- mands that operate when the device is not in debug mode (normal operation) and the commands that are disabled by programming the frp. table 95. on-chip debugger command summary debug command command byte enabled when not in debug mode? disabled by flash read protect option bit read ocd revision 00h yes ? reserved 01h ? ? read ocd status register 02h yes ? read runtime counter 03h ? ? write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes ? write program counter 06h ? disabled read program counter 07h ? disabled write register 08h ? only writes of the flash memory con- trol registers are allowed. additionally, only the mass erase command is allowed to be written to the flash con- trol register. read register 09h ? disabled write program memory 0ah ? disabled read program memory 0bh ? disabled write data memory 0ch ? yes read data memory 0dh ? ?
ps025113-1212 on-chip debugger commands z8 encore! ? f0830 series product specification 145 in the following bulleted list of ocd commands, data and commands sent from the host to the ocd are identified by dbg command/data . data sent from the ocd back to the host is identified by dbg data . read ocd revision (00h). the read ocd revision comman d determines the version of the on-chip debugger. if ocd commands are a dded, removed or changed this revision number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) read ocd status register (02h). the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] read runtime counter (03h). the runtime counter counts system clock cycles in between breakpoints. the 16-bit runtime counte r counts from 0000h and stops at the max- imum count of ffffh . the runtime counter is overwritte n during the writ e memory, read memory, write register, read register, read me mory crc, step instruc tion, stuff instruction and execute instru ction commands. dbg 03h dbg runtimecounter[15:8] dbg runtimecounter[7:0] write ocd control register (04h). the write ocd control register command writes the data that follows to the ocdctl register. when the flash read protect option bit is enabled, the dbgmode bit ( ocdctl [7]) can only be set to 1, it cannot be cleared to 0. to return the device to normal operat ing mode, the device must be reset. dbg 04h dbg ocdctl[7:0] read program memory crc 0eh ? ? reserved 0fh ? ? step instructio n 10h ? disabled stuff instruction 11h ? disabled execute instruction 12h ? disabled reserved 13h?ffh ? ? table 95. on-chip debugger command summary (continued) debug command command byte enabled when not in debug mode? disabled by flash read protect option bit
ps025113-1212 on-chip debugger commands z8 encore! ? f0830 series product specification 146 read ocd control register (05h). the read ocd control register command reads the value of the ocdctl register. dbg 05h? dbg ocdctl[7:0] write program counter (06h). the write program counter command, writes the data that follows to the ez8 cpu?s program counter (pc). if the device is not in debug mode or if the flash read protect option bit is enabled, the program counter (pc) values are discarded. dbg 06h? dbg programcounter[15:8] ? dbg programcounter[7:0] read program counter (07h). the read program counter command, reads the value in the ez8 cpus program counter (pc). if the devi ce is not in debug mode or if the flash read protect option bit is en abled, this command returns ffffh . dbg 07h? dbg programcounter[15:8] ? dbg programcounter[7:0] write register (08h). the write register command, writes data to the register file. data can be written 1?256 bytes at a time (256 bytes can be written by setting size to 0). if the device is not in debug mode, the address and data values are discarded. if the flash read protect option bit is enabled, only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h? dbg {4?h0,register address[11:8]} ? dbg register address[7:0] ? dbg size[7:0] ? dbg 1?256 data bytes read register (09h). the read register command, reads da ta from the register file. data can be read 1?256 bytes at a time (256 bytes ca n be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, this command returns ffh for all of the data values. dbg 09h? dbg {4?h0,register address[11:8] ? dbg register address[7:0] ? dbg size[7:0] ? dbg 1?256 data bytes write program me mory (0ah). the write program memory command, writes data to program memory. this command is equivalent to the ldc and ld ci instructions. data can be written 1?65536 bytes at a time (6 5536 bytes can be written by setting size to 0). the on-chip flash controller must be wr itten to and unlocked for the programming operation to occur. if the flash controller is not unlocked, the data is discarded. if the device is not in debug mode or if the flash read protect optio n bit is enabled, the data is discarded.
ps025113-1212 on-chip debugger commands z8 encore! ? f0830 series product specification 147 dbg 0ah? dbg program memory address[15:8] ? dbg program memory address[7:0] ? dbg size[15:8] ? dbg size[7:0] ? dbg 1?65536 data bytes read program memory (0bh). the read program memory command, reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1?65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, this com- mand returns ffh for the data. dbg 0bh? dbg program memory address[15:8] ? dbg program memory address[7:0] ? dbg size[15:8] ? dbg size[7:0] ? dbg 1?65536 data bytes write data memory (0ch). the write data memory comman d, writes data to data mem- ory. this command is equivalent to the ld e and ldei instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, the data is discarded. dbg 0ch? dbg data memory address[15:8] ? dbg data memory address[7:0] ? dbg size[15:8] ? dbg size[7:0] ? dbg 1?65536 data bytes read data memory (0dh). the read data memory command, reads from data memory. this command is equivalent to the lde and ldei instructions. data can be read from 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh? dbg data memory address[15:8] ? dbg data memory address[7:0] ? dbg size[15:8] ? dbg size[7:0] ? dbg 1?65536 data bytes read program memory crc (0eh). the read program memory crc command, com- putes and returns the cyclic re dundancy check (crc) of prog ram memory using the 16-bit crc-ccitt polynomial. if the device is no t in debug mode, this command returns ffffh for the crc value. unlike the other oc d read commands, there is a delay from issuing of the command until the ocd return s the data. the ocd reads program memory, calculates the crc value and returns the result. the delay is a function of program mem-
ps025113-1212 on-chip debugger control register definitions z8 encore! ? f0830 series product specification 148 ory size and is approximately equal to the sy stem clock period multiplied by the number of bytes in program memory. dbg 0eh? dbg crc[15:8] ? dbg crc[7:0] step instruction (10h). the step instruction command, st eps one assembly instruction at the current program counter (p c) location. if the device is not in debug mode or the flash read protect option bit is enab led, the ocd ignores this command. dbg 10h stuff instruction (11h). the stuff instruction command, steps one assembly instruction and allows specification of the first byte of the instruction. the rema ining 0?4 bytes of the instruction are read from program memory. th is command is useful for stepping over instructions where the first byte of the instru ction has been overwritten by a breakpoint. if the device is not in debug mode or the flash read protect option bit is enabled, the ocd ignores this command. dbg 11h? dbg opcode[7:0] execute instruction (12h). the execute instruction comman d allows sending an entire instruction to be executed to the ez8 cpu. th is command can also st ep over breakpoints. the number of bytes to send fo r the instruction depends on the opcode. if the device is not in debug mode or the flash read protect op tion bit is enabled, this command reads and discards one byte. dbg 12h? dbg 1?5 byte opcode on-chip debugger control register definitions this section describes the features of the on -chip debugger control and status registers. ocd control register the ocd control register controls the state of the on-chip debugger. this register is used to enter or exit debu g mode and to enable the brk instruction. it can also reset the z8 encore! f0830 series device. a reset and stop function can be achieved by writing 81h to this register. a reset and go function can be achieved by writing 41h to this register. if the device is in debug mode, a run function can be implemented by writing 40h to this register.
ps025113-1212 on-chip debugger control register definitions z8 encore! ? f0830 series product specification 149 table 96. ocd contro l register (ocdctl) bit 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 0 0000000 r/w r/wr/wr/wrrrrr/w bit description [7] ? dbgmode debug mode the device enters debug mode when this bi t is 1. when in debug mode, the ez8 cpu stops fetching new instructions. clearing this bit causes the ez8 cpu to restart. this bit is automatically set when a brk instruction is decoded and breakpoints are enabled. if the flash read protect option bit is enabled, this bit can only be cleared by resetting the device. it cannot be written to 0. 0 = the z8 encore! f0830 series device is operating in normal mode. 1 = the z8 encore! f0830 series device is in debug mode. [6] ? brken breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, breakpoints are disabled and the brk instruction behaves similar to an nop instruction. if this bit is 1 when a brk instruction is decoded, the dbgmode bit of the ocdctl register is automati- cally set to 1. 0 = breakpoints are disabled. 1 = breakpoints are enabled. [5] ? dbgack debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, the ocd sends a debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. [4:1] reserved these bits are reserved and must be programmed to 0000. [0] ? rst reset setting this bit to 1 resets the z8f04xa family device. the device goes through a normal power-on reset sequence with the exception that the on-chip debugger is not reset. this bit is automatically cleared to 0 at the end of the reset sequence. 0 = no effect. 1 = reset the flash read protect option bit device.
ps025113-1212 on-chip debugger control register definitions z8 encore! ? f0830 series product specification 150 ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. table 97. ocd status register (ocdstat) bit 7 6 5 4 3 2 1 0 field dbg halt frpenb reserved reset 00000000 r/w rrrrrrrr bit description [7] ? dbg debug status 0 = normal mode. 1 = debug mode. [6] ? halt halt mode 0 = not in halt mode. 1 = in halt mode. [5] ? frpenb flash read protect option bit enable 0 = frp bit enabled, that allows disabling of many ocd commands. 1 = frp bit has no effect. [4:0] reserved these bits are reserved and must be programmed to 00000.
ps025113-1212 oscillator control z8 encore! ? f0830 series product specification 151 oscillator control the z8 encore! f0830 series device uses five possible clocking schemes. each one of these is user-selectable. ? on-chip precision trimmed rc oscillator ? on-chip oscillator using off-chip crystal or resonator ? on-chip oscillator usin g external rc network ? external clock drive ? on-chip low precision watchdog timer oscillator in addition, z8 encore! f0830 series devices contain cloc k failure detectio n and recovery circuitry, allowing continued operation de spite a failure of the primary oscillator. operation this chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. a description of the specific oper ation of each oscillator is outlined further in this document. system clock selection the oscillator control block selects from the available clocks. table 98 describes each clock source and its usage.
ps025113-1212 operation z8 encore! ? f0830 series product specification 152 unintentional accesses to the o scillator control register can actually stop the chip by switching to a nonfunctioning oscillator. to prevent this condition, the oscillator control block employs a register unlocking/locking scheme. osc control register unlocking/locking to write the oscillator control register, un lock it by making two writes to the oscctl register with the values e7h followed by 18h . a third write to the oscctl register changes the value of the actual register and returns the register to a locked state. any other sequence of oscillator control register wr ites have no effect. th e values written to unlock the register must be ordered correctly, but are not necessarily co nsecutive. it is pos- sible to write to or read from other regist ers within the unlock ing/locking operation. table 98. oscillator configuration and selection clock source characteristics required setup internal precision rc oscillator ? 32.8 khz or 5.53 mhz ? 4% accuracy when trimmed ? no external components required ? unlock and write to the oscillator con- trol register (oscctl) to enable and select oscillator at either 5.53 mhz or ? 32.8 khz external crystal/res- onator ? 32 khz to 20 mhz ? very high accuracy (dependent on crystal or resonator used) ? requires external components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator, wait for it to stabilize and select as system clock (if the xtldis option bit has been de-asserted, no wa iting is required) external rc oscilla- tor ? 32 khz to 4 mhz ? accuracy dependent on exter- nal components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator and select as system clock external clock drive ? 0 to 20 mhz ? accuracy dependent on exter- nal clock source ? write gpio registers to configure pb3 pin for external clock function ? unlock and write oscctl to select external system clock ? apply external clock signal to gpio internal watchdog timer oscillator ? 10 khz nominal ? 40% accuracy; no external compo- nents required ? low power consumption ? enable wdt if not enabled and wait until wdt oscillator is operating. ? unlock and write to the oscillator con- trol register (oscctl) to enable and select oscillator caution:
ps025113-1212 operation z8 encore! ? f0830 series product specification 153 when selecting a new clock source, the primary oscillator failure detection circuitry and the watchdog timer oscillator failure circu itry must be disabled. if pofen and wofen are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator. the failure det ection circuitry can be enabled anytime after a successful write of oscsel in th e oscillator control register. the internal precision oscillator is enabled by default. if the user code changes to a differ- ent oscillator, it may be appr opriate to disable the ipo fo r power savings. disabling the ipo does not occur automatically. clock failure detection and recovery primary oscillator failure the z8f04xa family devices can generate no nmaskable interrupt-like events when the primary oscillator fails. to maintain system fu nction in this situatio n, the clock failure recovery circuitry automatically forces the watchdog timer o scillator to drive the system clock. the watchdog timer os cillator must be enabled to allow the recovery. although this oscillator runs at a much slower speed than the original system clock, the cpu contin- ues to operate, allowing execution of a cloc k failure vector and software routines that either remedy the oscillator failure or issue a failure alert. this au tomatic switch-over is not available if the watchdog timer is the primar y oscillator. it is also unavailable if the watchdog timer oscillator is di sabled, though it is not neces sary to enable the watchdog timer reset function outlined in the watc hdog timer chapter of this document. the primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 khz 50%. if an external signal is selected as the system oscillator, it is possible that a very slow but nonfailing clock can generate a failure condition. under these conditions, do not enable the cl ock failure circuitry (pofen must be deasserted in the oscctl register). watchdog timer failure in the event of failure of a watchdog time r oscillator, a similar nonmaskable interrupt- like event is issued. this even t does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a watchdog timer fa ilure, it is no longer possible to detect a primary oscillator failure. the failure detectio n circuitry does not function if the watchdog timer is used as the primary oscillator or if the watchdog timer oscillator has been dis- abled. for either of these cases, it is necessar y to disable the detection circuitry by deas- serting the wdfen bit of the oscctl register. the watchdog timer oscillator failure detection circuit coun ts system clocks while look- ing for a watchdog timer clock. the logic coun ts 8004 system clock cycles before deter- mining that a failure has occurred. the system clock rate determines the speed at which the watchdog timer failure is detected. a very slow system clock results in very slow detection times.
ps025113-1212 oscillator control register definitions z8 encore! ? f0830 series product specification 154 it is possible to disable the clock failure detection circuitry as well as all functioning clock sources. in this case, the z8 encore! f0830 series device ceases functioning and can only be recovered by power-on-reset. oscillator control register definitions the following section provides the bit definitions for the oscillator control register. oscillator control register the oscillator control register (oscctl) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes th e system clock. the oscillator control register must be un locked before writing. writing the two step sequence e7h followed by 18h to the oscillator control regi ster unlocks it. the register is locked at successful completion of a register write to the oscctl. figure 24 displays the oscillato r control clock switching flow. see table 117 on page 189 to review the waiting times of various oscillator circuits. table 99. oscillator control register (oscctl) bit 7 6 5 4 3 2 1 0 field inten xtlen wdten pofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f86h bit description [7] ? inten internal precision oscillator enable 1 = internal precision oscillator is enabled. 0 = internal precision oscillator is disabled. [6] ? xtlen crystal oscillator enable this setting overrides the gpio register control for pa0 and pa1. 1 = crystal oscillator is enabled. 0 = crystal oscillator is disabled. [5] ? wdten watchdog timer oscillator enable 1 = watchdog timer oscillator is enabled. 0 = watchdog timer os cillator is disabled. caution:
ps025113-1212 oscillator control register definitions z8 encore! ? f0830 series product specification 155 [4] ? pofen primary oscillator failure detection enable 1 = failure detection and recovery of primary oscilla tor is enabled. 0 = failure detection and recovery of primary oscilla tor is disabled. [3] ? wdfen watchdog timer oscillator failure detection enable 1 = failure detection of watchd og timer oscillator is enabled. 0 = failure detection of watchdog timer oscillator is disabled. [2:0] ? scksel system clock oscillator select 000 = internal precision oscillator fu nctions as system clock at 5.53 mhz. 001 = internal precision oscillator fu nctions as system clock at 32 khz. 010 = crystal oscillator or external rc oscillator functions as system clock. 011 = watchdog timer oscillato r functions as system clock. 100 = external clock signal on pb3 functions as system clock. 101 = reserved. 110 = reserved. 111 = reserved. bit description (continued)
ps025113-1212 oscillator control register definitions z8 encore! ? f0830 series product specification 156 figure 24. oscillator control clock switching flow chart normal running write to oscctl register: e7 18 to unlock oscctl register set bit7 in oscctl register and wait one nop instruction(wait 25 us if ipo bandgap is closed) osc is enabled? switch to ipo? switch to osc? switch to wdt? ipo is enabled? write to oscctl register: 000 to bits [2:0] set bit6 in oscctl register and wait 1.5ms@20mhz write to oscctl register: e7 18 to unlock oscctl register write to oscctl register: 010 to bits [2:0] wdt osc is enabled? write to oscctl register: e7 18 to unlock oscctl register write to oscctl register: 011 to bits [2:0] set bit5 in oscctl register and wait 50us yes no yes yes yes yes yes no no no no no
ps025113-1212 crystal oscillator z8 encore! ? f0830 series product specification 157 crystal oscillator the products in the z8 encore! f0830 series contain an on-chip crystal oscillator for use with external crystals with 32 khz to 20 mhz frequencies. in add ition, the oscillator sup- ports external rc networks with oscillation frequencies up to 4 mhz or ceramic resonators with frequencies up to 8 mhz. the on-chip crystal oscillator can be used to generate the primary system clock for the in ternal ez8 cpu and the majority of its on-chip peripherals. alternatively, the x in input pin can also accept a cmos-l evel clock input signal (32 khz? 20 mhz). if an external clock generator is used, the x out pin must remain unconnected. the on-chip crystal oscillator also contains a clock filter function. to see the settings for this clock filter, see table 90 on page 133. by default, however, this clock filter is dis- abled; therefore, no divide to the input cloc k (namely, the frequency of the signal on the x in input pin) can determine the frequency of the system clock when using the default set- tings. although the x in pin can be used as an input for an external clock generator, the clkin pin is better suited for such use. see the system clock selection section on page 151 for more information. operating modes the z8 encore! f0830 series products support the following four oscillator modes: ? minimum power for use with very low frequency crystals (32 khz to 1 mhz) ? medium power for use with medium frequency crystals or ceramic resonators (0.5 mhz to 8 mhz) ? maximum power for use with high frequ ency crystals (8 mhz to 20 mhz) ? on-chip oscillator configured for use with external rc networks (< 4 mhz) ? the oscillator mode is selected using user -programmable flash option bits. see the flash option bits chapter on page 124 for more information. crystal oscillator operation the xtldis flash option bit controls whether the crystal oscillator is enabled during reset. the crystal may later be disabled after reset if a new oscillato r has been selected as the system clock. if the crys tal is manually enabled afte r reset through the oscctl reg- note:
ps025113-1212 crystal oscillator operation z8 encore! ? f0830 series product specification 158 ister, the user code must wait at least 5000 ipo cycles for the crystal to stabilize. after this period, the crystal oscillator may be selected as the system clock. figure 25 displays a recommended configurat ion for connection with an external funda- mental-mode, parallel-resonant crystal operat ing at 20 mhz. recommended 20 mhz crys- tal specifications are provided in table 100. resistor r 1 is optional and limits total power dissipation by the crystal. prin ted circuit board layout must add no more than 4 pf of stray capacitance to either the x in or x out pins. if oscillation does not occur, reduce the values of capacitors c 1 and c 2 to decrease loading. figure 25. recommended 20 mhz crystal oscillator configuration table 100. recommended crystal oscillator specifications parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s )60 ? maximum load capacitance (c l )30 pfmaximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 22pf c1 = 22pf crystal xout xin on-chip oscillator r1 = 220 ?
ps025113-1212 oscillator operation with an external rc network z8 encore! ? f0830 series product specification 159 oscillator operation with an external rc network figure 26 displays a recommended configuratio n for connection with an external resistor- capacitor (rc) network. an external resistance value of 45 k ? is recommended for oscilla tor operation with an external rc network. the minimum resistan ce value to ensure operation is 40 k ? ?? the typical oscillator frequency can be estimated from the values of the resistor (r in k ? ) and capacitor (c in pf) elements using the following equation: figure 27 displays the typical (3.3 v and 25c) oscillator frequency as a function of the capacitor (c in pf) employed in the rc network assuming a 45 k ? external resistor. for very small values of c, the parasitic capacitance of the oscillator x in pin and the printed circuit board should be included in th e estimation of the oscillator frequency. it is possible to operate the rc oscillator usin g only the parasitic ca pacitance of the pack- age and printed circuit board. to minimize sensitivity to external parasitics, external capacitance values in excess of 20 pf are recommended. figure 26. connecting the on-chip osci llator to an external rc network c x in r vdd oscillator frequency (khz) 1 6 ? 10 0.4 r c ?? ?? 4c ? ?? + --------------------------------------------------------- =
ps025113-1212 oscillator operation with an external rc network z8 encore! ? f0830 series product specification 160 when using the external rc oscillator mode , the oscillator can stop oscillating if the power supply drops below 2.7 v but before it drops to the volta ge brown-out thresh- old. the oscillator resum es oscillation when the supp ly voltage exceeds 2.7 v. figure 27. typical rc oscillator frequency as a function of external capacitance with a 45 k ? resistor 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 c (pf) frequency (khz) caution:
ps025113-1212 internal precision oscillator z8 encore! ? f0830 series product specification 161 internal precision oscillator the internal precision oscillator (ipo) is de signed for use without external components. the user can either manually trim the osc illator for a nonstandard frequency or use the automatic factory-trimmed version to achieve a 5.53 mhz frequency with 4% accuracy and 45%~55% duty cycle over the operating te mperature and supply voltage of the device. the maximum start-up time of the ip o is 25 s. ipo features include: ? on-chip rc oscillator that does not require external components ? output frequency of either 5.53 mhz or 32.8 khz (contains both a fast and a slow mode) ? trimming possible through flash option bits, with user override ? elimination of crystals or ceramic resonato rs in applications where high timing accu- racy is not required operation the internal oscillator is an rc relaxation oscillator with a minimized sensitivity to power supply variations. by using ratio-tracking thresholds, the effect of power supply voltage is cancelled out. the dominant source of oscilla tor error is the absolute variance of chip- level fabricated components, such as capacitor s. an 8-bit trimming re gister, incorporated into the design, compensates fo r absolute variation of oscilla tor frequency. on ce trimmed, the oscillator frequency is stable and does no t require subsequent calibration. trimming was performed during manufacturing and is not necessary for the user to repeat unless a frequency other than 5.53 mhz (fast mode ) or 32.8 khz (slow mode) is required. the user can power down the ipo block for minimum system power. by default, the oscillator is configured through the flash option bits. however, the user code can override these trim values, as described in the trim bit address space section on page 129 . select one of two frequencies for the oscillator: 5.53 mhz or 32.8 khz, using the oscsel bits described in the oscillator control chapter on page 151. note:
ps025113-1212 ez8 cpu instruction set z8 encore! ? f0830 series product specification 162 ez8 cpu instruction set this chapter describes the following feat ures of the ez8 cpu instruction set: assembly language programming introduction : see page 162 assembly language syntax : see page 163 ez8 cpu instruction notation : see page 164 ez8 cpu instruction classes : see page 166 ez8 cpu instruction summary : see page 171 assembly language programming introduction the ez8 cpu assembly language provides a me ans for writing an application program without concern for actual memory addresses or machine instruction formats. a program written in assembly language is called a sour ce program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (op codes and operands) to represent the instructions themselves. the op codes identify the instruction while the operan ds represent memory locations, registers or immediate data values. each assembly language program consists of a series of symbolic commands called state- ments. each statement contains labels , operations, operands and comments. labels can be assigned to a particular instru ction step in a source program. the label iden- tifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, these pseudo -ops are interpreted as directiv es that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. the object code is executed by the ez8 cpu. an example segment of an assembly language prog ram is provided in the following example.
ps025113-1212 assembly language syntax z8 encore! ? f0830 series product specification 163 assembly language s ource program example assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as destination, source . after assembly, the object code usually reflects the operands in the order source, destination , but ordering is op code-dependent. the following examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. example 1 if the contents of registers 43h and 08h are added and the result is stored in 43h , the assembly syntax and resulting object code is: jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction (jp start) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a loa d (ld) instruction with two operands. the first operand, ; working register r4, is the destination. the second operand, ; working register r7, is the source. the contents of r7 is ; written into r4. ld 234h, #%01 ; ano ther load (ld) instruction with two operands. ; the first operand, extended mode register address 234h, ; identifies the destination. the second operand, immediate data ; value 01h, is the source. the value 01h is written into the ; register at address 234h. table 101. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst)
ps025113-1212 ez8 cpu instruction notation z8 encore! ? f0830 series product specification 164 example 2 in general, when an instructio n format requires an 8-bit register address, the address can specify any register location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if the contents of register 43h and working register r8 are added and the result is stored in 43h , the assembly syntax and resulting object code is: see the device specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and de scription sections, the operands, condition codes, status flags and address modes are repr esented by the notational shorthand listed in table 103. table 102. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst) table 103. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see condition codes overview in the ez8 cpu user manual. da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. represents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0 ?15 ir indirect register @reg reg. represents a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12 or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15
ps025113-1212 ez8 cpu instruction notation z8 encore! ? f0830 series product specification 165 table 104 contains additional symbols that are used throughout the instruction summary and instruction set description sections. assignment of a value is indicated by an arrow, as shown in the following example. dst dst + src r register reg reg. represents a number in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to ? 128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12 or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represents a number in the range of 00h to ffh x indexed #index the register or register pair to be indexed is off- set by the signed index value (#index) in a +127 to ? ?128 range. table 104. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix table 103. notational shorthand (continued) notation description operand range
ps025113-1212 ez8 cpu instruction classes z8 encore! ? f0830 series product specification 166 this example indicates that the source data is added to the destina tion data; the result is stored in the destination location. ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift ? tables 105 through 112 contain the instructions belonging to each group and the number of operands required for each instruction. some inst ructions appear in more than one table as these instructions can be considered as a sub set of more than one category. within these tables, the source operand is identified as src , the destination operand is dst and a condi- tion code is cc . table 105. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment
ps025113-1212 ez8 cpu instruction classes z8 encore! ? f0830 series product specification 167 incw dst increment word mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract using extended addressing table 106. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test comp lement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 107. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto- increment addresses ldei dst, src load external data to/from data memory and auto- increment addresses table 105. arithmetic instructions (continued) mnemonic operands instruction
ps025113-1212 ez8 cpu instruction classes z8 encore! ? f0830 series product specification 168 table 108. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set regi ster pointer stop ? stop mode wdt ? watchdog timer refresh table 109. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto- increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto- increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing
ps025113-1212 ez8 cpu instruction classes z8 encore! ? f0830 series product specification 169 table 110. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 111. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 112. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry
ps025113-1212 ez8 cpu instruction classes z8 encore! ? f0830 series product specification 170 rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 112. rotate and shift instructions (continued) mnemonic operands instruction
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 171 ez8 cpu instruction summary table 113 summarizes the ez8 cpu instructio ns. the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch and the number of cpu clock cycles required for the instruction execution. table 113. ez8 cpu instruction summary assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 * * * * 0 * 2 3 rir 13 2 4 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 * * * * 0 * 4 3 er im 19 4 3 add dst, src dst dst + src r r 02 * * * * 0 * 2 3 rir 03 2 4 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 * * * * 0 * 4 3 er im 09 4 3 note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 172 and dst, src dst dst and src r r 52 ? * * 0 ? ? 2 3 rir 53 2 4 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 ? * * 0 ? ? 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ?????? 1 2 bclr bit, dst dst[bit] 0re2?**0??22 bit p, bit, dst dst[bit] pre 2? * * 0 ? ?22 brk debugger break 00 ? ? ? ? ? ? 1 1 bset bit, dst dst[bit] 1re 2? * * 0 ? ?22 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 ? ? 2 2 btj p, bit, src, dst if src[bit] = p ? pc pc + x r f6 ?????? 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 ? pc pc + x r f6 ?????? 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 ? pc pc + x r f6 ?????? 3 3 ir f7 3 4 call dst sp sp ?2 ? @sp pc ? pc dst irr d4 ?????? 2 6 da d6 3 3 ccf c ~c ef *?????- 1 2 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 173 clr dst dst 00h r b0 ?????? 2 2 ir b1 2 3 com dst dst ~dst r 60 ? * * 0 ? ? 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * ? ? 2 3 rir a3 2 4 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * ? ? 3 3 rir1f a3 3 4 rr 1f a4 4 3 rir 1f a5 4 4 rim 1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * ? ? 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * ? ? 4 3 er im a9 4 3 da dst dst da(dst) r 40 * * * x ? ? 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 ? * * * ? ? 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 ? * * * ? ? 2 5 irr 81 2 6 di irqctl[7] 0 8f ?????? 1 2 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 174 djnz dst, ra dst dst ? 1 ? if dst ? 0 ? pc pc + x r 0a?fa ?????? 2 3 ei irqctl[7] 1 9f ?????? 1 2 halt halt mode 7f ?????? 1 2 inc dst dst dst + 1 r 20 ? * * ? ? ? 2 2 ir 21 2 3 r0 e ? f e 12 incw dst dst dst + 1 rr a0 ? * * * ? ? 2 5 irr a1 2 6 iret flags @sp ? sp sp + 1 ? pc @sp ? sp sp + 2 ? irqctl[7] 1 bf ****** 1 5 jp dst pc dst da 8d ?????? 3 2 irr c4 2 3 jp cc, dst if cc is true ? pc dst da 0d?fd ? ? ? ? ? ? 3 2 jr dst pc pc + x da 8b ?????? 2 2 jr cc, dst if cc is true ? pc pc + x da 0b?fb ? ? ? ? ? ? 2 2 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 175 ld dst, rc dst src r im 0c?fc ? ? ? ? ? ? 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 2 3 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 ldc dst, src dst src r irr c2 ? ? ? ? ? ? 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src ? r r + 1 ? rr rr + 1 ir irr c3 ?????? 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ? ? ? ? ? ? 2 5 irr r 92 2 5 ldei dst, src dst src ? r r + 1 ? rr rr + 1 ir irr 83 ?????? 2 9 irr ir 93 2 9 ldwx dst, src dst src er er 1fe8 ?????? 5 4 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 176 ldx dst, src dst src r er 84 ?????? 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ?????? 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] ? dst[15:8] * dst[7:0] rr f4 ?????? 2 8 nop no operation 0f ? ? ? ? ? ? 1 2 or dst, src dst dst or src r r 42 ? * * 0 ? ? 2 3 rir 43 2 4 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 ? * * 0 ? ? 4 3 er im 49 4 3 pop dst dst @sp ? sp sp + 1 r 50 ?????? 2 2 ir 51 2 3 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 177 popx dst dst @sp sp sp + 1 er d8 ?????? 3 2 push src sp sp ? 1 @sp src r 70 ?????? 2 2 ir 71 2 3 im if70 3 2 pushx src sp sp ? 1 ? @sp src er c8 ?????? 3 2 rcf c 0 cf 0????? 1 2 ret pc @sp ? sp sp + 2 af ?????? 1 4 rl dst r 90 * * * * ? ? 2 2 ir 91 2 3 rlc dst r 10 * * * * ? ? 2 2 ir 11 2 3 rr dst r e0 ****?? 2 2 ir e1 2 3 rrc dst r c0 * * * * ? ? 2 2 ir c1 2 3 sbc dst, src dst dst ? src - c r r 32 * * * * 1 * 2 3 rir 33 2 4 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 * * * * 1 * 4 3 er im 39 4 3 scf c 1 df 1????? 1 2 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 178 sra dst r d0 * * * 0 ? ? 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * ? ? 3 2 ir 1f c1 3 3 srp src rp src im 01 ?????? 2 2 stop stop mode 6f ?????? 1 2 sub dst, src dst dst ? src r r 22 * * * * 1 * 2 3 rir 23 2 4 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst dst ? src er er 28 * * * * 1 * 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x ? ? 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 2 3 rir 63 2 4 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 ? * * 0 ? ? 4 3 er im 69 4 3 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps025113-1212 ez8 cpu instruction summary z8 encore! ? f0830 series product specification 179 tm dst, src dst and src r r 72 ? * * 0 ? ? 2 3 rir 73 2 4 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 ? * * 0 ? ? 4 3 er im 79 4 3 trap vector sp sp ? 2 ? @sp pc ? sp sp ? 1 ? @sp flags ? pc @vector vec- tor f2 ?????? 2 6 wdt 5f ?????? 1 2 xor dst, src dst dst xor src r r b2 ? * * 0 ? ? 2 3 rir b3 2 4 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 ? * * 0 ? ? 4 3 er im b9 4 3 table 113. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op code(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps025113-1212 op code maps z8 encore! ? f0830 series product specification 180 op code maps a description of the opcode map data and the abbreviations are provided in figure 28. table 114 on page 181 lists opcode map abbreviations. figure 28. op code map cell description cp 3.3 r2,r1 a 4 op code lower nibble second operand after assembly first operand after assembly op code upper nibble instruction cycles fetch cycles
ps025113-1212 op code maps z8 encore! ? f0830 series product specification 181 table 114. op code map abbreviations abbreviation description abbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displace- ment r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps025113-1212 op code maps z8 encore! ? f0830 series product specification 182 figures 29 and 30 provide information about each of the ez8 cpu instructions. figure 29. first op code map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.1 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 op code see 2nd map
ps025113-1212 op code maps z8 encore! ? f0830 series product specification 183 figure 30. second op code map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3.2 pus ldwx 5, 4 er2,er1
ps025113-1212 electrical characteristics z8 encore! ? f0830 series product specification 184 electrical characteristics the data in this chapter represents all known data prior to qualification and characteriza- tion of the f0830 series of products, and is therefore subject to change. additional electri- cal characteristics may be found in the individual chapters of this document. absolute maximum ratings stresses greater than those listed in table 1 15 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, tie unused in puts to one of the supply voltages (v dd or v ss ). table 115. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias 0 +105 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v voltage on v dd pin with respect to v ss ?0.3 +3.6 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma 20-pin packages maximum ratings at 0c to 70c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma 28-pin packages maximum ratings at 0c to 70c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma
ps025113-1212 dc characteristics z8 encore! ? f0830 series product specification 185 dc characteristics table 116 lists the dc characteristics of th e z8 encore! f0830 series products. all volt- ages are referenced to v ss , the primary system ground. table 116. dc characteristics symbol parameter t a = 0c to +70c t a = ?40c to +105c units conditions min typ max min typ max v dd supply voltage 2.7 ? 3.6 v p ower supply noise not to exceed 100 mv peak to peak v il1 low level input voltage ?0.3 ? 0.3*v d d v for all input pins except reset . v il2 low level input voltage ?0.3 ? 0.8 v for reset . v ih1 high level input voltage 2.0 ? 5.5 v for all input pins without analog or oscillator func- tion. v ih2 high level input voltage 2.0 ? v dd +0. 3 v for those pins with ana- log or oscillator function. v ol1 low level output voltage ??0.4vi ol = 2 ma; v dd = 3.0 v ? high output drive dis- abled. v oh1 high level output voltage 2.4 ? ? v i oh = ?2 ma; v dd = 3.0 v ? high output drive dis- abled. v ol2 low level output voltage ??0.6vi ol = 20 ma; v dd = 3.3 v ? high output drive enabled. v oh2 high level output voltage 2.4 ? ? v i oh = ?20 ma; v dd = 3.3 v ? high output drive enabled. i il input leakage current ?5 ? +5 a v dd = 3.6 v; ? v in = v dd or v ss 1 i tl tristate leakage current ?5 ? +5 a v dd = 3.6 v notes: 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production. 3. see figure 31 for halt mode current.
ps025113-1212 dc characteristics z8 encore! ? f0830 series product specification 186 i led controlled current drive 1.5 3 4.5 ma see gpio section on led description 2.8 7 10.5 ma 7.8 13 19.5 ma 12 20 30 ma c pad gpio port pad capacitance ?8.0 2 ?pftbd c xin xin pad capacitance ?8.0 2 ?pftbd c xout xout pad capacitance ?9.5 2 ?pftbd i pu weak pull-up current 50 120 220 a v dd = 2.7 - 3.6 v icch 3 supply current in halt mode tbd ma tbd iccs supply current in stop mode 28 a without watchdog timer running table 116. dc characteristics (continued) symbol parameter t a = 0c to +70c t a = ?40c to +105c units conditions min typ max min typ max notes: 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production. 3. see figure 31 for halt mode current.
ps025113-1212 dc characteristics z8 encore! ? f0830 series product specification 187 figure 31 displays the typical current consump tion while operating at 25 oc, 3.3 v, versus the system clock frequency in halt mode. figure 31. i cc versus system clock frequency (halt mode)
ps025113-1212 dc characteristics z8 encore! ? f0830 series product specification 188 figure 32 displays the typical current consum ption versus the system clock frequency in normal mode. figure 32. i cc versus system clock frequency (normal mode)
ps025113-1212 ac characteristics z8 encore! ? f0830 series product specification 189 ac characteristics the section provides information about the ac characteristics and timing. all ac timing information assumes a standard load of 50 pf on all outputs. table 117. ac characteristics symbol parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 to 3.6 v t a = ?40c to +105c units conditions min max min max f sysclk system clock fre- quency ? 20.0 mhz read-only from flash memory 0.03276 8 20.0 mhz program or erasure of the flash memory f xtal crystal oscillator frequency 1.0 20.0 mhz system clock frequen- cies below the crystal oscillator minimum require an external f ipo internal precision oscillator frequency 0.03276 8 5.5296 mhz oscillator is not adjust- able over the entire range. user may select min or max value only. f ipo internal precision oscillator frequency 5.31 5.75 mhz high speed with trim- ming f ipo internal precision oscillator frequency 4.15 6.91 mhz high speed without trimming f ipo internal precision oscillator frequency 30.7 33.3 khz low speed with trim- ming f ipo internal precision oscillator frequency 24 40 khz low speed without trimming t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50 ns t xinl system clock low time 20 30 ns t clk = 50 ns
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 190 on-chip peripheral ac and dc electrical characteristics t xinr system clock rise time ?3nst clk = 50 ns t xinf system clock fall time ?3nst clk = 50 ns t xtalset crystal oscillator setup time ? 30,000 cycle crystal oscillator cycles t iposet internal precision oscillator startup time ? 25 s startup time after enable t wdtset wdt startup time ? 50 s startup time after reset table 118. power-on reset and voltage brown- out electrical characteristics and timing symbol parameter t a = 0c to +70c t a = ?40c to +105c units conditions min typ max min typ 1 max v por power-on reset voltage threshold 2.20 2.45 2.70 v v dd = v por (default vbo trim) v vbo voltage brown-out reset voltage threshold 2.15 2.40 2.65 v v dd = v vbo (default vbo trim) v por to v vbo hysteresis 50 75 mv starting v dd voltage to ensure valid power-on reset. ?v ss ?v t ana power-on reset analog delay ?50? sv dd > v por ; t por digital reset delay follows t ana note: 1 data in the typical column is from characterization at 3.3 v and 0c. these values are provided for design guid- ance only and are not tested in production. table 117. ac characteristics (continued) symbol parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 to 3.6 v t a = ?40c to +105c units conditions min max min max
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 191 t por power-on reset digital delay tbd 13 tbd s 66 internal preci- sion oscillator cycles t por power-on reset digital delay tbd 8 tbd ms 5000 internal pre- cision oscillator cycles t smr stop mode recovery with crystal oscillator disabled tbd 13 tbd s 66 internal preci- sion oscillator cycles t smr stop mode recovery with crystal oscillator enabled tbd 8 tbd ms 5000 internal pre- cision oscillator cycles t vbo voltage brown-out pulse rejection period ?10? s v dd < v vbo to gen- erate a reset. t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms table 118. power-on reset and voltage brown- out electrical characteristics and timing symbol parameter t a = 0c to +70c t a = ?40c to +105c units conditions min typ max min typ 1 max note: 1 data in the typical column is from characterization at 3.3 v and 0c. these values are provided for design guid- ance only and are not tested in production.
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 192 table 119. flash memory electr ical characteristics and timing parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 to 3.6 v t a = ?40c to +105c units notes min typ max min typ max flash byte read time 50 ? ? ns flash byte program time 20 ? ? s flash page erase time 50 ? ? ms flash mass erase time 50 ? ? ms writes to single address before next erase ??2 flash row program time ? ? 8 ms cumulative pro- gram time for single row cannot exceed limit before next erase. this parame- ter is only an issue when bypassing the flash controller. data retention 10 ? ? years 25c endurance 10,000 ? ? cycles program/erase cycles table 120. watchdog timer electrical characteristics and timing symbol parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 - 3.6 v t a = ?40c to +105c units conditions min typ max min typ max active power consumption 23a f wdt wdt oscillator frequency 2.5 5 7.5 khz
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 193 for every 200 writes, a maintenance operation is necessary. in this rare occurrence, the write can take up to 58 ms to complete. table 121. nonvolatile data storage parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 to 3.6 v t a = ?40c to +105c units notes min typ max min typ max nvds byte read time 71 ? 258 s with system clock at 20 mhz nvds byte pro- gram time 126 ? 136 s with system clock at 20 mhz data retention 10 ? ? years 25c endurance 100,000 ? ? cycles cumulative write cycles for entire memory table 122. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 to 3.6 v t a = ?40c to +105c units conditions min typ max min typ max resolution ? 10 ? bits differential nonlinearity (dnl) 1 ?1 ? +4 lsb integral nonlinearity (inl) 1 ?5 ? +5 lsb gain error 15 lsb offset error ?15 ? 15 lsb pdip package ?9 ? 9 lsb other packages v ref on chip reference 1.9 2.0 2.1 v active power consumption 4m a power down current 1a note: 1 when the input voltage is lower than 20 mv, the conversion error is out of spec. note:
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 194 z in input impedance 10 m ? v in input voltage range 0 2.0 v internal refer- ence 00.9*vd d external refer- ence conversion time 11.9 s 20 mhz (adc clock) input bandwidth 500 khz wake up time 0.02 ms internal refer- ence 10 external refer- ence input clock duty 45 50 55 maximum input clock frequency 20 mhz table 123. comparator electrical characteristics symbol parameter v dd = 2.7 to 3.6v t a = 0c to +70c v dd = 2.7 to 3.6v t a = ?40c to +105c units conditions min typ max min typ max v os input dc offset 5 mv v cref programmable internal reference voltage range 0 1.8 v user-program- mable in 200 mv step v cref programmable internal reference voltage 0.92 1.0 1.08 v default (cmp0[reflvl] =5h) t prop propagation delay 100 ns v hys input hysteresis 8 mv table 122. analog-to-digital converter electr ical characteristics and timing (continued) symbol parameter v dd = 2.7 to 3.6 v t a = 0c to +70c v dd = 2.7 to 3.6 v t a = ?40c to +105c units conditions min typ max min typ max note: 1 when the input voltage is lower than 20 mv, the conversion error is out of spec.
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 195 general purpose i/o port input data sample timing figure 33 displays timing of the gpio port input sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is available to the ez8 cpu on the second rising clock edge following the change of the port value. figure 33. port input sample timing table 124. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to x in rise setup time (not pictured) 5 ? t h_port x in rise to port inpu t transition hold time (not pictured) 0 ? t smr gpio port pin pulse width to ensure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk port pin port value changes to 0 0 latched into port input input value port input data register latch clock data register port input data read on data bus port input data register value 0 read by ez8
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 196 general purpose i/o port output timing figure 34 and table 125 provide timing information for the gpio port pins. figure 34. gpio port output timing table 125. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 197 on-chip debugger timing figure 35 and table 126 provide timing info rmation for the dbg pin. the dbg pin tim- ing specifications assume a 4 ns maximum rise and fall time. figure 35. on-chip debugger timing table 126. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 5 ? t 4 dbg to xin rise input hold time 5 ? xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps025113-1212 on-chip peripheral ac and dc electrical z8 encore! ? f0830 series product specification 198 table 127. power consumption reference table category block power consumption typical maximum logic cpu/peripherals @ 20 mhz 5 ma flash flash @ 20 mhz 12 ma analog adc @ 20 mhz 4 ma 4.5 ma ipo 350 a 400 a comparator @ 10 mhz 330 a 450 a por & vbo 120 a 150 a wdt oscillator 2 a 3 a osc @ 20 mhz 600 a 900 a clock filter 120 ? a 150 a note: the values in this table are s ubject to change after characterization. figure 36. flash current diagram
ps025113-1212 packaging z8 encore! ? f0830 series product specification 199 packaging zilog?s f0830 series of mcus includes the z8f0130, z8f0131, Z8F0230, z8f0231, z8f1232 and z8f1233 devices, which are available in the following packages: ? 20-pin quad flat no -lead package (qfn) ? 20-pin small outline integrated circuit package (soic) ? 20-pin plastic dual -inline package (pdip) ? 20-pin small shrink outline package (ssop) ? 28-pin quad flat no -lead package (qfn) ? 28-pin small outline integrated circuit package (soic) ? 28-pin plastic dual -inline package (pdip) ? 28-pin small shrink outline package (ssop) ? current diagrams for each of the se packages are published in zilog?s packaging product specification (ps0072) , which is available free for do wnload from the zilog website.
ps025113-1212 ordering information z8 encore! ? f0830 series product specification 200 ordering information order your f0830 series products from zilog using the part numbers shown in table 128. for more information about ordering, please consult your local zilog sales office. the sales location page on the zilog website lists all regional offices. table 128. z8 encore! xp f0830 series ordering matrix part number flash ram nvds adc channels description z8 encore! f0830 series mcus with 12 kb flash standard temperature: 0c to 70c z8f1232sh020sg 12 kb 256 no 7 soic 20-pin z8f1232hh020sg 12 kb 256 no 7 ssop 20-pin z8f1232ph020sg 12 kb 256 no 7 pdip 20-pin z8f1232qh020sg 12 kb 256 no 7 qfn 20-pin z8f1233sh020sg 12 kb 256 no 0 soic 20-pin z8f1233hh020sg 12 kb 256 no 0 ssop 20-pin z8f1233ph020sg 12 kb 256 no 0 pdip 20-pin z8f1233qh020sg 12 kb 256 no 0 qfn 20-pin z8f1232sj020sg 12 kb 256 no 8 soic 28-pin z8f1232hj020sg 12 kb 256 no 8 ssop 28-pin z8f1232pj020sg 12 kb 256 no 8 pdip 28-pin z8f1232qj020sg 12 kb 256 no 8 qfn 28-pin z8f1233sj020sg 12 kb 256 no 0 soic 28-pin z8f1233hj020sg 12 kb 256 no 0 ssop 28-pin z8f1233pj020sg 12 kb 256 no 0 pdip 28-pin z8f1233qj020sg 12 kb 256 no 0 qfn 28-pin extended temperature: ?40c to 105c z8f1232sh020eg 12 kb 256 no 7 soic 20-pin z8f1232hh020eg 12 kb 256 no 7 ssop 20-pin z8f1232ph020eg 12 kb 256 no 7 pdip 20-pin z8f1232qh020eg 12 kb 256 no 7 qfn 20-pin z8f1233sh020eg 12 kb 256 no 0 soic 20-pin z8f1233hh020eg 12 kb 256 no 0 ssop 20-pin z8f1233ph020eg 12 kb 256 no 0 pdip 20-pin
ps025113-1212 ordering information z8 encore! ? f0830 series product specification 201 z8f1233qh020eg 12 kb 256 no 0 qfn 20-pin z8f1232sj020eg 12 kb 256 no 8 soic 28-pin z8f1232hj020eg 12 kb 256 no 8 ssop 28-pin z8f1232pj020eg 12 kb 256 no 8 pdip 28-pin z8f1232qj020eg 12 kb 256 no 8 qfn 28-pin z8f1233sj020eg 12 kb 256 no 0 soic 28-pin z8f1233hj020eg 12 kb 256 no 0 ssop 28-pin z8f1233pj020eg 12 kb 256 no 0 pdip 28-pin z8f1233qj020eg 12 kb 256 no 0 qfn 28-pin z8 encore! f0830 with 8 kb flash standard temperature: 0c to 70c z8f0830sh020sg 8 kb 256 yes 7 soic 20-pin z8f0830hh020sg 8 kb 256 yes 7 ssop 20-pin z8f0830ph020sg 8 kb 256 yes 7 pdip 20-pin z8f0830qh020sg 8 kb 256 yes 7 qfn 20-pin z8f0831sh020sg 8 kb 256 yes 0 soic 20-pin z8f0831hh020sg 8 kb 256 yes 0 ssop 20-pin z8f0831ph020sg 8 kb 256 yes 0 pdip 20-pin z8f0831qh020sg 8 kb 256 yes 0 qfn 20-pin z8f0830sj020sg 8 kb 256 yes 8 soic 28-pin z8f0830hj020sg 8 kb 256 yes 8 ssop 28-pin z8f0830pj020sg 8 kb 256 yes 8 pdip 28-pin z8f0830qj020sg 8 kb 256 yes 8 qfn 28-pin z8f0831sj020sg 8 kb 256 yes 0 soic 28-pin z8f0831hj020sg 8 kb 256 yes 0 ssop 28-pin z8f0831pj020sg 8 kb 256 yes 0 pdip 28-pin z8f0831qj020sg 8 kb 256 yes 0 qfn 28-pin extended temperature: ?40c to 105c z8f0830sh020eg 8 kb 256 yes 7 soic 20-pin z8f0830hh020eg 8 kb 256 yes 7 ssop 20-pin z8f0830ph020eg 8 kb 256 yes 7 pdip 20-pin z8f0830qh020eg 8 kb 256 yes 7 qfn 20-pin z8f0831sh020eg 8 kb 256 yes 0 soic 20-pin table 128. z8 encore! xp f0830 series ordering matrix part number flash ram nvds adc channels description
ps025113-1212 ordering information z8 encore! ? f0830 series product specification 202 z8f0831hh020eg 8 kb 256 yes 0 ssop 20-pin z8f0831ph020eg 8 kb 256 yes 0 pdip 20-pin z8f0831qh020eg 8 kb 256 yes 0 qfn 20-pin z8f0830sj020eg 8 kb 256 yes 8 soic 28-pin z8f0830hj020eg 8 kb 256 yes 8 ssop 28-pin z8f0830pj020eg 8 kb 256 yes 8 pdip 28-pin z8f0830qj020eg 8 kb 256 yes 8 qfn 28-pin z8f0831sj020eg 8 kb 256 yes 0 soic 28-pin z8f0831hj020eg 8 kb 256 yes 0 ssop 28-pin z8f0831pj020eg 8 kb 256 yes 0 pdip 28-pin z8f0831qj020eg 8 kb 256 yes 0 qfn 28-pin z8 encore! f0830 with 4 kb flash standard temperature: 0c to 70c z8f0430sh020sg 4 kb 256 yes 7 soic 20-pin z8f0430hh020sg 4 kb 256 yes 7 ssop 20-pin z8f0430ph020sg 4 kb 256 yes 7 pdip 20-pin z8f0430qh020sg 4 kb 256 yes 7 qfn 20-pin z8f0431sh020sg 4 kb 256 yes 0 soic 20-pin z8f0431hh020sg 4 kb 256 yes 0 ssop 20-pin z8f0431ph020sg 4 kb 256 yes 0 pdip 20-pin z8f0431qh020sg 4 kb 256 yes 0 qfn 20-pin z8f0430sj020sg 4 kb 256 yes 8 soic 28-pin z8f0430hj020sg 4 kb 256 yes 8 ssop 28-pin z8f0430pj020sg 4 kb 256 yes 8 pdip 28-pin z8f0430qj020sg 4 kb 256 yes 8 qfn 28-pin z8f0431sj020sg 4 kb 256 yes 0 soic 28-pin z8f0431hj020sg 4 kb 256 yes 0 ssop 28-pin z8f0431pj020sg 4 kb 256 yes 0 pdip 28-pin z8f0431qj020sg 4 kb 256 yes 0 qfn 28-pin extended temperature: ?40c to 105c z8f0430sh020eg 4 kb 256 yes 7 soic 20-pin z8f0430hh020eg 4 kb 256 yes 7 ssop 20-pin z8f0430ph020eg 4 kb 256 yes 7 pdip 20-pin table 128. z8 encore! xp f0830 series ordering matrix part number flash ram nvds adc channels description
ps025113-1212 ordering information z8 encore! ? f0830 series product specification 203 z8f0430qh020eg 4 kb 256 yes 7 qfn 20-pin z8f0431sh020eg 4 kb 256 yes 0 soic 20-pin z8f0431hh020eg 4 kb 256 yes 0 ssop 20-pin z8f0431ph020eg 4 kb 256 yes 0 pdip 20-pin z8f0431qh020eg 4 kb 256 yes 0 qfn 20-pin z8f0430sj020eg 4 kb 256 yes 8 soic 28-pin z8f0430hj020eg 4 kb 256 yes 8 ssop 28-pin z8f0430pj020eg 4 kb 256 yes 8 pdip 28-pin z8f0430qj020eg 4 kb 256 yes 8 qfn 28-pin z8f0431sj020eg 4 kb 256 yes 0 soic 28-pin z8f0431hj020eg 4 kb 256 yes 0 ssop 28-pin z8f0431pj020eg 4 kb 256 yes 0 pdip 28-pin z8f0431qj020eg 4 kb 256 yes 0 qfn 28-pin z8 encore! f0830 with 2 kb flash standard temperature: 0c to 70c Z8F0230sh020sg 2 kb 256 yes 7 soic 20-pin Z8F0230hh020sg 2 kb 256 yes 7 ssop 20-pin Z8F0230ph020sg 2 kb 256 yes 7 pdip 20-pin Z8F0230qh020sg 2 kb 256 yes 7 qfn 20-pin z8f0231sh020sg 2 kb 256 yes 0 soic 20-pin z8f0231hh020sg 2 kb 256 yes 0 ssop 20-pin z8f0231ph020sg 2 kb 256 yes 0 pdip 20-pin z8f0231qh020sg 2 kb 256 yes 0 qfn 20-pin Z8F0230sj020sg 2 kb 256 yes 8 soic 28-pin Z8F0230hj020sg 2 kb 256 yes 8 ssop 28-pin Z8F0230pj020sg 2 kb 256 yes 8 pdip 28-pin Z8F0230qj020sg 2 kb 256 yes 8 qfn 28-pin z8f0231sj020sg 2 kb 256 yes 0 soic 28-pin z8f0231hj020sg 2 kb 256 yes 0 ssop 28-pin z8f0231pj020sg 2 kb 256 yes 0 pdip 28-pin z8f0231qj020sg 2 kb 256 yes 0 qfn 28-pin table 128. z8 encore! xp f0830 series ordering matrix part number flash ram nvds adc channels description
ps025113-1212 ordering information z8 encore! ? f0830 series product specification 204 extended temperature: ?40c to 105c Z8F0230sh020eg 2 kb 256 yes 7 soic 20-pin Z8F0230hh020eg 2 kb 256 yes 7 ssop 20-pin Z8F0230ph020eg 2 kb 256 yes 7 pdip 20-pin Z8F0230qh020eg 2 kb 256 yes 7 qfn 20-pin z8f0231sh020eg 2 kb 256 yes 0 soic 20-pin z8f0231hh020eg 2 kb 256 yes 0 ssop 20-pin z8f0231ph020eg 2 kb 256 yes 0 pdip 20-pin z8f0231qh020eg 2 kb 256 yes 0 qfn 20-pin Z8F0230sj020eg 2 kb 256 yes 8 soic 28-pin Z8F0230hj020eg 2 kb 256 yes 8 ssop 28-pin Z8F0230pj020eg 2 kb 256 yes 8 pdip 28-pin Z8F0230qj020eg 2 kb 256 yes 8 qfn 28-pin z8f0231sj020eg 2 kb 256 yes 0 soic 28-pin z8f0231hj020eg 2 kb 256 yes 0 ssop 28-pin z8f0231pj020eg 2 kb 256 yes 0 pdip 28-pin z8f0231qj020eg 2 kb 256 yes 0 qfn 28-pin z8 encore! f0830 with 1kb flash standard temperature: 0c to 70c z8f0130sh020sg 1 kb 256 yes 7 soic 20-pin z8f0130hh020sg 1 kb 256 yes 7 ssop 20-pin z8f0130ph020sg 1 kb 256 yes 7 pdip 20-pin z8f0130qh020sg 1 kb 256 yes 7 qfn 20-pin z8f0131sh020sg 1 kb 256 yes 0 soic 20-pin z8f0131hh020sg 1 kb 256 yes 0 ssop 20-pin z8f0131ph020sg 1 kb 256 yes 0 pdip 20-pin z8f0131qh020sg 1 kb 256 yes 0 qfn 20-pin z8f0130sj020sg 1 kb 256 yes 8 soic 28-pin z8f0130hj020sg 1 kb 256 yes 8 ssop 28-pin z8f0130pj020sg 1 kb 256 yes 8 pdip 28-pin z8f0130qj020sg 1 kb 256 yes 8 qfn 28-pin z8f0131sj020sg 1 kb 256 yes 0 soic 28-pin z8f0131hj020sg 1 kb 256 yes 0 ssop 28-pin table 128. z8 encore! xp f0830 series ordering matrix part number flash ram nvds adc channels description
ps025113-1212 part number suffix designations z8 encore! ? f0830 series product specification 205 part number suffix designations zilog part numbers consist of a number of components, as indicated in the following example. example. part number z8f0830sh020sg is an 8-bit 20 mhz flash mcu with 8 kb pro- gram memory and equipped with adc and nvds in a 20-pin soic package, operating within a 0oc to +70oc temperature ra nge and built using lead-free solder. z8f0131pj020sg 1 kb 256 yes 0 pdip 28-pin z8f0131qj020sg 1 kb 256 yes 0 qfn 28-pin extended temperature: ?40c to 105c z8f0130sh020eg 1 kb 256 yes 7 soic 20-pin z8f0130hh020eg 1 kb 256 yes 7 ssop 20-pin z8f0130ph020eg 1 kb 256 yes 7 pdip 20-pin z8f0130qh020eg 1 kb 256 yes 7 qfn 20-pin z8f0131sh020eg 1 kb 256 yes 0 soic 20-pin z8f0131hh020eg 1 kb 256 yes 0 ssop 20-pin z8f0131ph020eg 1 kb 256 yes 0 pdip 20-pin z8f0131qh020eg 1 kb 256 yes 0 qfn 20-pin z8f0130sj020eg 1 kb 256 yes 8 soic 28-pin z8f0130hj020eg 1 kb 256 yes 8 ssop 28-pin z8f0130pj020eg 1 kb 256 yes 8 pdip 28-pin z8f0130qj020eg 1 kb 256 yes 8 qfn 28-pin z8f0131sj020eg 1 kb 256 yes 0 soic 28-pin z8f0131hj020eg 1 kb 256 yes 0 ssop 28-pin z8f0131pj020eg 1 kb 256 yes 0 pdip 28-pin z8f0131qj020eg 1 kb 256 yes 0 qfn 28-pin zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg opto-isol ated usb smart cable accessory kit table 128. z8 encore! xp f0830 series ordering matrix part number flash ram nvds adc channels description
ps025113-1212 part number suffix designations z8 encore! ? f0830 series product specification 206 z8 f 08 30 s h 020 s g environmental flow g = green plastic packaging compound temperature range s = standard, 0c to 70c ? e = extended, ?40c to +105c speed 020 = 20 mhz pin count* h = 20 j = 28 package* p = pdip q = qfn ? s = soic h = ssop device type 30 = equipped with adc and with nvds. 31 = equipped without adc and with nvds. 32 = equipped with adc and without nvds (12 k version only). 33 = equipped without adc and without nvds (12 k version only). memory size 12 = 12 kb flash 08 = 8 kb flash 04 = 4 kb flash 02 = 2 kb flash 01 = 1 kb flash memory type f = flash device family z8 = zilog?s 8-bit microcontroller
ps025113-1212 part number suffix designations z8 encore! ? f0830 series product specification 207 table 129 lists the pin count by package. table 129. package and pin count description package pin count 20 28 pdip ? qfn ? soic ? ssop ?
ps025113-1212 general purpose ram z8 encore! ? f0830 series product specification 208 appendix a. register tables for the reader?s convenience, this appendix lists all f0830 series registers numerically by hexadecimal address. general purpose ram in the f0830 series, the 000?eff hexadecimal address range is partitioned for general- purpose random access memory, as follows. hex addresses: 000?0ff this address range is reserved for general-purpose register f ile ram. for more details, see the register file section on page 14. hex addresses: 100?eff this address range is reserved. timer 0 for more information about these timer control registers, see the timer control register definitions section on page 83. hex address: f00 table 130. timer 0 high byte register (t0h) bit 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f00h
ps025113-1212 timer 0 z8 encore! ? f0830 series product specification 209 hex address: f01 hex address: f02 hex address: f03 hex address: f04 table 131. timer 0 low byte register (t0l) bit 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f01h table 132. timer 0 reload high byte register (t0rh) bit 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f02h table 133. timer 0 reload low byte register (t0rl) bit 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f03h table 134. timer 0 pwm high byte register (t0pwmh) bit 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f04h
ps025113-1212 timer 0 z8 encore! ? f0830 series product specification 210 hex address: f05 hex address: f06 hex address: f07 hex address: f08 table 135. timer 0 pwm low byte register (t0pwml) bit 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f05h table 136. timer 0 control register 0 (t0ctl0) bit 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f06h table 137. timer 0 control register 1 (t0ctl1) bit 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f07h table 138. timer 1 high byte register (t1h) bit 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f08h
ps025113-1212 timer 0 z8 encore! ? f0830 series product specification 211 hex address: f09 hex address: f0a hex address: f0b hex address: f0c table 139. timer 1 low byte register (t1l) bit 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f09h table 140. timer 1 reload high byte register (t1rh) bit 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f0ah table 141. timer 1 reload low byte register (t1rl) bit 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f0bh table 142. timer 1 pwm high byte register (t1pwmh) bit 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f0ch
ps025113-1212 timer 0 z8 encore! ? f0830 series product specification 212 hex address: f0d hex address: f0e hex address: f0f hex addresses: f10?f6f this address range is reserved. table 143. timer 1 pwm low byte register (t1pwml) bit 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f0dh table 144. timer 1 control register 0 (t1ctl0) bit 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f0eh table 145. timer 1 control register 1 (t1ctl1) bit 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f0fh
ps025113-1212 analog-to-digital converter z8 encore! ? f0830 series product specification 213 analog-to-digital converter for more information about these adc registers, see the adc control register defini- tions section on page 101. hex address: f70 table 146. adc control register 0 (adcctl0) bit 7 6 5 4 3 2 1 0 field start reserved refen adce n reserved anain[2:0] reset 00000000 r/w r/w1 r/w r/w r/w r/w r/w r/w r/w address f70h bit description [7] ? start adc start/busy 0 = writing to 0 has no effect; reading a 0 indica tes that the adc is available to begin a conver- sion. 1 = writing to 1 starts a conversion; reading a 1 indicates that a conversion is currently in prog- ress. [6] this bit is reserved and must be programmed to 0. [5] ? refen reference enable 0 = internal reference voltage is disabled allowing an external reference voltage to be used by the adc. 1 = internal reference voltage for the adc is enabled. the internal reference voltage can be measured on the v ref pin. [4] ? adcen adc enable 0 = adc is disabled for low power operation. 1 = adc is enabled for normal use. [3] this bit is reserved and must be programmed to 0. [2:0] ? anain analog input select 000 = ana0 input is selected for analog to digital conversion. 001 = ana1 input is selected for analog to digital conversion. 010 = ana2 input is selected for analog to digital conversion. 011 = ana3 input is selected for analog to digital conversion. 100 = ana4 input is selected for analog to digital conversion. 101 = ana5 input is selected for analog to digital conversion. 110 = ana6 input is selected for analog to digital conversion. 111 = ana7 input is selected for analog to digital conversion.
ps025113-1212 analog-to-digital converter z8 encore! ? f0830 series product specification 214 hex address: f71 this address range is reserved. hex address: f72 hex address: f73 table 147. adc data high byte register (adcd_h) bit 7 6 5 4 3 2 1 0 field adcdh reset x r/w r address f72h bit description [7:0] adc high byte 00h?ffh = the last conversion output is held in the data registers until the next adc conver- sion is completed. table 148. adc data low bits register (adcd_l) bit 7 6 5 4 3 2 1 0 field adcdl reserved reset xx r/w rr address f73h bit ? position description [7:6] adc low bits 00?11b = these bits are the two least significant bits of the 10-bit adc output. these bits are undefined after a reset. the low bits are latched into this register whenever the adc data high byte register is read. [5:0] reserved these bits are reserved and must be programmed to 000000.
ps025113-1212 analog-to-digital converter z8 encore! ? f0830 series product specification 215 hex address: f74 hex address: f75 hex addresses: f77?f7f this address range is reserved. table 149. adc sample settling time (adcsst) bit 7 6 5 4 3 2 1 0 field reserved sst reset 0 1111 r/w rr/w address f74h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3:0] ? sst sample settling time 0h?fh = number of system clock pe riods to meet 0.5 s minimum. table 150. adc sample time (adcst) bit 7 6 5 4 3 2 1 0 field reserved st reset 0 111111 r/w r/w r/w address f75h bit description [7:6] reserved this register is reserved and must be programmed to 0. [5:0] ? st sample/hold time 0h?fh = number of system clock periods to meet 1 s minimum.
ps025113-1212 low power control z8 encore! ? f0830 series product specification 216 low power control for more information about the power control register, see the power control register definitions section on page 31. hex address: f80 hex address: f81 this address range is reserved. led controller for more information about th e led drive registers, see the gpio control register defi- nitions section on page 39. hex address: f82 table 151. power control register 0 (pwrctl0) bit 7 6 5 4 3 2 1 0 field reserved vbo reserved re served comp reserved reset 10001000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f80h table 152. led drive enable (leden) bit 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f82h
ps025113-1212 oscillator control z8 encore! ? f0830 series product specification 217 hex address: f83 hex address: f84 hex address: f85 this address range is reserved. oscillator control for more information about the osc illator control registers, see the oscillator control register definitions section on page 154. hex address: f86 table 153. led drive level high register (ledlvlh) bit 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f83h table 154. led drive level low register (ledlvll) bit 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f84h table 155. oscillator control register (oscctl) bit 7 6 5 4 3 2 1 0 field inten xtlen wdten pofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f86h
ps025113-1212 comparator 0 z8 encore! ? f0830 series product specification 218 hex addresses: f87?f8f this address range is reserved. comparator 0 for more information about the comparator register, see the comparator control regis- ter definitions section on page 107. hex address: f90 hex addresses: f91?fbf this address range is reserved. interrupt controller for more information ab out the interrupt control registers, see the interrupt control reg- ister definitions section on page 57. hex address: fc0 table 156. comparator control register (cmp0) bit 7 6 5 4 3 2 1 0 field reserved innsel reflvl reserved reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f90h table 157. interrupt request 0 register (irq0) bit 7 6 5 4 3 2 1 0 field reserved t1i t0i reserved rese rved reserved reserved adci reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc0h
ps025113-1212 interrupt controller z8 encore! ? f0830 series product specification 219 hex address: fc1 hex address: fc2 hex address: fc3 hex address: fc4 table 158. irq0 enable hi gh bit register (irq0enh) bit 7 6 5 4 3 2 1 0 field reserved t1enh t0enh reserved re served reserved reserved adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc1h table 159. irq0 enable lo w bit register (irq0enl) bit 7 6 5 4 3 2 1 0 field reserved t1enl t0enl reserved re served reserved reserved adcenl reset 00000000 r/w r r/w r/w r/w r/w r r r/w address fc2h table 160. interrupt request 1 register (irq1) bit 7 6 5 4 3 2 1 0 field pa7i pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc3h table 161. irq1 enable hi gh bit register (irq1enh) bit 7 6 5 4 3 2 1 0 field pa7enh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc4h
ps025113-1212 interrupt controller z8 encore! ? f0830 series product specification 220 hex address: fc5 hex address: fc6 hex address: fc7 hex address: fc8 table 162. irq1 enable lo w bit register (irq1enl) bit 7 6 5 4 3 2 1 0 field pa7enl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc5h table 163. interrupt request 2 register (irq2) bit 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc6h table 164. irq2 enable hi gh bit register (irq2enh) bit 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc7h table 165. irq2 enable lo w bit register (irq2enl) bit 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc8h
ps025113-1212 interrupt controller z8 encore! ? f0830 series product specification 221 hex addresses: fc9?fcc this address range is reserved. hex address: fcd hex address: fce hex address: fcf table 166. interrupt edge select register (irqes) bit 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fcdh table 167. shared interrupt select register (irqss) bit 7 6 5 4 3 2 1 0 field reserved pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fceh table 168. interrupt control register (irqctl) bit 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr address fcfh
ps025113-1212 gpio port a z8 encore! ? f0830 series product specification 222 gpio port a for more information about the gpio registers, see the gpio control register definitions section on page 39. hex address: fd0 hex address: fd1 hex address: fd2 table 169. port a gpio address register (paaddr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd0h table 170. port a control registers (pactl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd1h table 171. port a input data registers (pain) bit 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr address fd2h
ps025113-1212 gpio port a z8 encore! ? f0830 series product specification 223 hex address: fd3 hex address: fd4 hex address: fd5 hex address: fd6 table 172. port a output data register (paout) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd3h table 173. port b gpio address register (pbaddr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd4h table 174. port b control registers (pbctl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd5h table 175. port b input data registers (pbin) bit 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr address fd6h
ps025113-1212 gpio port a z8 encore! ? f0830 series product specification 224 hex address: fd7 hex address: fd8 hex address: fd9 hex address: fda table 176. port b output data register (pbout) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd7h table 177. port c gpio address register (pcaddr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd8h table 178. port c control registers (pcctl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd9h table 179. port c input data registers (pcin) bit 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr address fdah
ps025113-1212 gpio port a z8 encore! ? f0830 series product specification 225 hex address: fdb hex address: fdc hex address: fdd hex address: fde this address range is reserved. table 180. port c output data register (pcout) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fdbh table 181. port d gpio address register (pdaddr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fdch table 182. port d control registers (pdctl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fddh
ps025113-1212 watchdog timer z8 encore! ? f0830 series product specification 226 hex address: fdf hex addresses: fe0?fef this address range is reserved. watchdog timer for more information about the wa tchdog timer registers, see the watchdog timer con- trol register definitions section on page 95. hex address: ff0 the watchdog timer control register address is shared with the read-only reset status register. table 183. port d output data register (pdout) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fdfh table 184. watchdog timer control register (wdtctl) bit 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww address ff0h table 185. reset status register (rststat) bit 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset see table 12 on page 2900000 r/w rrrrrrrr address ff0h
ps025113-1212 watchdog timer z8 encore! ? f0830 series product specification 227 hex address: ff1 hex address: ff2 hex address: ff3 hex addresses: ff4?ff5 this address range is reserved. table 186. watchdog timer reload upper byte register (wdtu) bit 7 6 5 4 3 2 1 0 field wdtu reset 00000000 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff1h note: *read returns the current wdt count val ue; write sets the appropriate reload value. table 187. watchdog timer reload high byte register (wdth) bit 7 6 5 4 3 2 1 0 field wdth reset 00000100 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff2h note: *read returns the current wdt count val ue; write sets the appropriate reload value. table 188. watchdog timer reload low byte register (wdtl) bit 7 6 5 4 3 2 1 0 field wdtl reset 00000000 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* address ff3h note: *read returns the current wdt count val ue; write sets the appropriate reload value.
ps025113-1212 trim bit control z8 encore! ? f0830 series product specification 228 trim bit control for more information about the trim bit control registers, see the flash option bit con- trol register definitions section on page 126. hex address: ff6 hex address: ff7 flash memory controller for more information about the flash control registers, see the flash control register definitions section on page 118. hex address: ff8 table 189. trim bit address register (trmadr) bit 7 6 5 4 3 2 1 0 field trmadr - trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff6h table 190. trim bit data register (trmdr) bit 7 6 5 4 3 2 1 0 field trmdr - trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff7h table 191. flash control register (fctl) bit 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww address ff8h
ps025113-1212 flash memory controller z8 encore! ? f0830 series product specification 229 hex address: ff8 hex address: ff9 the flash page select register is shared with the flash sector protect register. hex address: ffa table 192. flash status register (fstat) bit 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr address ff8h table 193. flash page select register (fps) bit 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h table 194. flash sector protect register (fprot) bit 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h table 195. flash frequency high byte register (ffreqh) bit 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ffah
ps025113-1212 flash memory controller z8 encore! ? f0830 series product specification 230 hex address: ffb table 196. flash frequency low byte register (ffreql) bit 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w address ffbh
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 231 index symbols @ 165 # 165 % 165 numerics 10-bit adc 4 a absolute maximum ratings 184 ac characteristics 189 adc 166 block diagram 99 overview 98 adc channel register 1 (adcctl) 102 adc data high byte register (adcdh) 103 adc data low bit register (adcdl) 103, 104, 105 adcx 166 add 166 add - extended addressing 166 add with carry 166 add with carry - extended addressing 166 additional symbols 165 address space 14 addx 166 analog block/pwm signal synchronization 100 analog block/pwm signal zynchronization 100 analog signals 11 analog-to-digital converter overview 98 and 169 andx 169 architecture voltage measurements 98 arithmetic instructions 166 assembly language programming 162 assembly language syntax 163 b b 165 b 164 bclr 167 binary number suffix 165 bit 167 bit 164 clear 167 manipulation instructions 167 set 167 set or clear 167 swap 167 test and jump 169 test and jump if non-zero 169 test and jump if zero 169 bit jump and test if non-zero 166 bit swap 169 block diagram 3 block transfer instructions 167 brk 169 bset 167 bswap 167, 169 btj 169 btjnz 166, 169 btjz 169 c calibration and compensa tion, motor control mea- surements 101 call procedure 169 capture mode 89, 90 capture/compare mode 89 cc 164 ccf 168 characteristics, electrical 184 clear 168 clr 168 com 169 compare 89
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 232 compare - extended addressing 166 compare mode 89 compare with carry 166 compare with carry - ex tended addressing 166 complement 169 complement carry flag 167, 168 condition code 164 continuous mode 89 control registers 14, 17 counter modes 89 cp 166 cpc 166 cpcx 166 cpu and peripheral overview 4 cpu control instructions 168 cpx 166 current measurement architecture 98 operation 99 customer feedback form 239 customer information 239 d da 164, 166 data memory 16 dc characteristics 185 debugger, on-chip 139 dec 166 decimal adjust 166 decrement 166 decrement and jump non-zero 169 decrement word 166 decw 166 destination operand 165 device, port availability 33 di 168 direct address 164 disable interrupts 168 djnz 169 dst 165 e ei 168 electrical characteristics 184 gpio input data sample timing 195 watch-dog timer 194 electrical noise 98 enable interrupt 168 er 164 extended addressing register 164 external pin reset 25 ez8 cpu features 4 ez8 cpu instruction classes 166 ez8 cpu instruction notation 164 ez8 cpu instruction set 162 ez8 cpu instruction summary 171 f fctl register 119, 126, 127, 228 features, z8 encore! 1 first opcode map 182 flags 165 flags register 165 flash controller 4 option bit address space 127 option bit configuration - reset 124 program memory address 0000h 127 program memory address 0001h 128 flash memory 108 byte programming 116 code protection 114 configurations 108 control register definitions 118, 126 controller bypass 117 flash control register 119, 126, 127, 228 flash option bits 115 flash status register 120 flow chart 113 frequency high and low byte registers 123 mass erase 117 operation 112 operation timing 114 page erase 117
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 233 page select register 121, 122 fps register 121, 122 fstat register 120 g gated mode 89 general-purpose i/o 33 gpio 4, 33 alternate functions 34 architecture 34 control register definitions 39 input data sample timing 195 interrupts 39 port a-c pull-up enable sub-registers 46, 47, 48 port a-h address registers 40 port a-h alternate fu nction sub-registers 42 port a-h control registers 41 port a-h data direction sub-registers 41 port a-h high drive enable sub-registers 44 port a-h input data registers 49 port a-h output control sub-registers 43 port a-h output data registers 50, 51 port a-h stop mode re covery sub-registers 45 port availability by device 33 port input timing 195 port output timing 196 h h 165 halt 168 halt mode 31, 168 hexadecimal number prefix/suffix 165 i im 164 immediate data 164 immediate operand prefix 165 inc 166 increment 166 increment word 167 incw 167 indexed 165 indirect address prefix 165 indirect register 164 indirect register pair 164 indirect working register 164 indirect working register pair 164 instruction set, ez8 cpu 162 instructions adc 166 adcx 166 add 166 addx 166 and 169 andx 169 arithmetic 166 bclr 167 bit 167 bit manipulation 167 block transfer 167 brk 169 bset 167 bswap 167, 169 btj 169 btjnz 166, 169 btjz 169 call 169 ccf 167, 168 clr 168 com 169 cp 166 cpc 166 cpcx 166 cpu control 168 cpx 166 da 166 dec 166 decw 166 di 168 djnz 169 ei 168 halt 168 inc 166 incw 167 iret 169
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 234 jp 169 ld 168 ldc 168 ldci 167, 168 lde 168 ldei 167 ldx 168 lea 168 load 168 logical 169 mult 167 nop 168 or 169 orx 169 pop 168 popx 168 program control 169 push 168 pushx 168 rcf 167, 168 ret 169 rl 169 rlc 169 rotate and shift 169 rr 170 rrc 170 sbc 167 scf 167, 168 sra 170 srl 170 srp 168 stop 168 sub 167 subx 167 swap 170 tcm 167 tcmx 167 tm 167 tmx 167 trap 169 watch-dog timer refresh 168 xor 169 xorx 169 instructions, ez8 classes of 166 interrupt control register 67 interrupt controller 53 architecture 53 interrupt assertion types 56 interrupt vectors and priority 56 operation 55 register definitions 57 software interrupt assertion 57 interrupt edge select register 65 interrupt request 0 register 58 interrupt request 1 register 59 interrupt request 2 register 60 interrupt return 169 interrupt vector listing 53 ir 164 ir 164 iret 169 irq0 enable high and low bit registers 60 irq1 enable high and low bit registers 62 irq2 enable high and low bit registers 63 irr 164 irr 164 j jp 169 jump, conditional, relative, and relative conditional 169 l ld 168 ldc 168 ldci 167, 168 lde 168 ldei 167, 168 ldx 168 lea 168 load 168 load constant 167 load constant to/from program memory 168 load constant with auto-increment addresses 168 load effective address 168 load external data 168
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 235 load external data to/fro m data memory and auto- increment addresses 167 load external to/from data memory and auto-incre- ment addresses 168 load instructions 168 load using extended addressing 168 logical and 169 logical and/extended addressing 169 logical exclusive or 169 logical exclusive or/extended addressing 169 logical instructions 169 logical or 169 logical or/extended addressing 169 low power modes 30 m master interrupt enable 55 memory data 16 program 15 mode capture 89, 90 capture/compare 89 continuous 89 counter 89 gated 89 one-shot 89 pwm 89, 90 modes 89 motor control measurements adc control register definitions 101 calibration and compensation 101 interrupts 101 overview 98 mult 167 multiply 167 n noise, electrical 98 nop (no operation) 168 notation b 164 cc 164 da 164 er 164 im 164 ir 164 ir 164 irr 164 irr 164 p 164 r 165 r 164 ra 165 rr 165 rr 165 vector 165 x 165 notational shorthand 164 o ocd architecture 139 auto-baud detector/generator 142 baud rate limits 142 block diagram 139 breakpoints 143 commands 144 control register 148 data format 142 dbg pin to rs-232 interface 140 debug mode 141 debugger break 169 interface 140 serial errors 143 status register 150 timing 197 ocd commands execute instruction (12h) 148 read data memory (0dh) 147 read ocd control re gister (05h) 146 read ocd revision (00h) 145 read ocd status register (02h) 145 read program counter (07h) 146 read program memory (0bh) 147
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 236 read program memory crc (0eh) 147 read register (09h) 146 read runtime counter (03h) 145 step instruction (10h) 148 stuff instruction (11h) 148 write data memory (0ch) 147 write ocd control register (04h) 145 write program counter (06h) 146 write program memory (0ah) 146 write register (08h) 146 on-chip debugger (ocd) 139 on-chip debugger signals 12 on-chip oscillator 157 one-shot mode 89 opcode map abbreviations 181 cell description 180 first 182 second after 1fh 183 operation 100 current measurement 99 voltage measurement timing diagram 100 operational description 21, 30, 33, 53, 68, 92, 98, 106, 108, 124, 134, 139, 151, 157, 161 or 169 ordering information 200 orx 169 oscillator signals 12 p p 164 packaging 199 part selection guide 2 pc 165 peripheral ac and dc electrical characteristics 190 pin characteristics 13 pin descriptions 7 polarity 164 pop 168 pop using extended addressing 168 popx 168 port availability, device 33 port input timing (gpio) 195 port output timing, gpio 196 power supply signals 12 power-on reset (por) 23 program control instructions 169 program counter 165 program memory 15 push 168 push using extended addressing 168 pushx 168 pwm mode 89, 90 pxaddr register 40, 222, 223, 224, 225 pxctl register 41, 222, 223, 224, 225 r r 165 r 164 ra register address 165 rcf 167, 168 register 165 flash control (fctl) 119, 126, 127, 228 flash high and low byte (ffreqh and fre- eql) 123 flash page select (fps) 121, 122 flash status (fstat) 120 gpio port a-h address (pxaddr) 40, 222, 223, 224, 225 gpio port a-h alternate function sub-registers 42 gpio port a-h control address (pxctl) 41, 222, 223, 224, 225 gpio port a-h data direction sub-registers 41 ocd control 148 ocd status 150 watch-dog timer control (wdtctl) 95, 107, 154, 217, 218, 226 watchdog timer control (wdtctl) 29 watch-dog timer reload high byte (wdth) 227 watchdog timer reload high byte (wdth) 96 watch-dog timer reload low byte (wdtl) 227 watchdog timer reload low byte (wdtl) 97 watch-dog timer reload upper byte (wdtu) 227
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 237 watchdog timer reload upper byte (wdtu) 96 register file 14 register pair 165 register pointer 165 registers adc channel 1 102 adc data high byte 103 adc data low bit 103, 104, 105 reset and stop mode characteristics 22 and stop mode recovery 21 carry flag 167 sources 23 ret 169 return 169 rl 169 rlc 169 rotate and shift instuctions 169 rotate left 169 rotate left through carry 169 rotate right 170 rotate right th rough carry 170 rp 165 rr 165, 170 rr 165 rrc 170 s sbc 167 scf 167, 168 second opcode map after 1fh 183 set carry flag 167, 168 set register pointer 168 shift right arithmatic 170 shift right logical 170 signal descriptions 11 software trap 169 source operand 165 sp 165 sra 170 src 165 srl 170 srp 168 stack pointer 165 stop 168 stop mode 30, 168 stop mode recovery sources 26 using a gpio port pin transition 27, 28 using watch-dog timer time-out 27 sub 167 subtract 167 subtract - extended addressing 167 subtract with carry 167 subtract with carry - extended addressing 167 subx 167 swap 170 swap nibbles 170 symbols, additional 165 t table 134. power consumption reference table 197 tcm 167 tcmx 167 test complement under mask 167 test complement under mask - extended addressing 167 test under mask 167 test under mask - extended addressing 167 tiing diagram, voltage measurement 100 timer signals 11 timers 68 architecture 68 block diagram 69 capture mode 77, 78, 89, 90 capture/compare mode 81, 89 compare mode 79, 89 continuous mode 70, 89 counter mode 71, 72 counter modes 89 gated mode 80, 89 one-shot mode 69, 89 operating mode 69 pwm mode 74, 75, 89, 90 reading the timer count values 82
ps025113-1212 p r e l i m i n a r y index z8 encore! ? f0830 series product specification 238 reload high and low byte registers 85 timer control register definitions 83 timer output signal operation 82 timers 0-3 control registers 87, 88 high and low byte registers 83, 86 tm 167 tmx 167 trap 169 v vector 165 voltage brown-out reset (vbr) 24 voltage measurement timing diagram 100 w watch-dog timer approximate time-out delay 92 approximate time-out delays 92, 106, 134, 151, 161 cntl 24 control register 95, 154 electrical characteristics and timing 194 interrupt in noromal operation 93 interrupt in stop mode 93 operation 92, 106, 134, 151, 161 refresh 93 reload unlock sequence 94 reload upper, high and low registers 96 reset 25 reset in normal operation 94 reset in stop mode 94 time-out response 93 watchdog timer refresh 168 wdtctl register 29, 95, 107, 154, 217, 218, 226 wdth register 96, 227 wdtl register 97, 227 working register 164 working register pair 165 wtdu register 96, 227 x x 165 xor 169 xorx 169 z z8 encore! block diagram 3 features 1 part selection guide 2
ps025113-1212 customer support z8 encore! ? f0830 series product specification 239 customer support to share comments, get your technical questio ns answered or report issues you may be experiencing with our products, please visit zilog?s technical support page at ? http://support.zilog.com . to learn more about this product, find additio nal documentation or to discover other facets about zilog product offerings, plea se visit the zilog knowledge base at http://zilog.com/ kb or consider participating in the zilog forum at http://zilog.com/forum . this publication is subject to replacement by a later edition. to determine whether a later edition exists, please vis it the zilog website at http://www.zilog.com .

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